Method for fabricating SOI device

• US 20060258110A1
• Filed: 05/11/2005
• Published: 11/16/2006
• Est. Priority Date: 05/11/2005
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Pelella, Mario M.
• Granted Patent: US 7,361,534 B2
• Time in Patent Office: Days
• US Class Current: 438/311
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 29/66128 Planar diodes
• CPC Class Codes: H01L 29/8611 Planar PN junction diodes

Abstract

A method is provided for fabricating a semiconductor on insulator (SOI) device. The method includes, in one embodiment, providing a monocrystalline silicon substrate having a monocrystalline silicon layer overlying the substrate and separated therefrom by a dielectric layer. A gate electrode material is deposited and patterned to form a gate electrode and a spacer. Impurity determining dopant ions are implanted into the monocrystalline silicon layer using the gate electrode as an ion implant mask to form spaced apart source and drain regions in the monocrystalline silicon layer and into the monocrystalline silicon substrate using the spacer as an ion implant mask to form spaced apart device regions in the monocrystalline substrate. Electrical contacts are then formed that contact the spaced apart device regions.

Claims

1. A method for fabricating a semiconductor on insulator (SOI) device having a monocrystalline silicon layer overlying a monocrystalline silicon substrate and separated therefrom by a dielectric layer, the method comprising the steps of:

depositing a gate electrode material overlying the monocrystalline silicon layer;

patterning the gate electrode material td form a gate electrode and a spacer;

ion implanting impurity determining dopant ions into the monocrystalline silicon layer using the gate electrode as an ion implant mask to form spaced apart source and drain regions in the monocrystalline silicon layer;

ion implanting impurity determining dopant ions into the monocrystalline silicon substrate using the spacer as an ion implant mask to form spaced apart device regions in the monocrystalline substrate; and

electrically contacting the spaced apart device regions.

2. The method of claim 1 wherein the step of patterning the gate electrode material comprises the steps of:

photolithographically patterning and etching the gate electrode material using a minimum lithography feature size; and

thereafter reducing the width of the gate electrode and spacer by isotropically etching the gate electrode material.

3. The method of claim 1 further comprising the step of ion implanting a well region in the monocrystalline silicon substrate within which the spaced apart device regions are formed.

4. The method of claim 1 wherein the step of ion implanting to form spaced apart device regions comprises the steps of:

ion implanting an N-type impurity determining dopant to form an N-type device region; and

ion implanting a P-type impurity determining dopant to form a P-type device region.

5. The method of claim 4 wherein the step of ion implanting an N-type impurity determining dopant further comprises the step of ion implanting an N-type impurity determining dopant to form N-channel source and drain regions in the monocrystalline silicon layer and the step of ion implanting a P-type impurity determining dopant further comprises the step of ion implanting a P-type impurity determining dopant to form P-channel source and drain regions in the monocrystalline silicon layer.

6. A method for fabricating a semiconductor on insulator (SOI) device having a monocrystalline silicon layer overlying a monocrystalline silicon substrate and separated therefrom by a dielectric layer, the method comprising the steps of:

forming a dielectric isolation region extending through the monocrystalline silicon layer to the dielectric layer;

depositing a layer of gate electrode material overlying the monocrystalline silicon layer and the dielectric isolation region;

patterning the layer of gate electrode material to simultaneously form a gate electrode overlying the monocrystalline silicon layer and a spacer overlying the dielectric isolation region;

etching the dielectric isolation region and the dielectric layer using the spacer as an etch mask; and

ion implanting impurity determining dopant ions to form spaced apart device regions in the monocrystalline silicon substrate using the spacer as an ion implantation mask.

7. The method of claim 6 wherein the step of patterning the layer of gate electrode material comprises the step of patterning the layer of gate electrode material to form a gate electrode and a spacer each have a minimum width.

8. The method of claim 6 wherein the step of ion implanting impurity determining dopant ions to form spaced apart device regions comprises the steps of:

ion implanting a P-type region to form an anode of a substrate diode; and

ion implanting an N-type region to form a cathode of a substrate diode.

9. The method of claim 6 further comprising the step of forming a metal silicide layer on the spaced apart device regions.

10. The method of claim 9 further comprising the steps of:

depositing a layer of insulating material overlying the metal silicide layer;

planarizing the layer of insulating material;

etching openings through the layer of insulating material to expose the metal silicide layer; and

forming electrical contacts in the openings to electrically contact the device regions.

11. The method of claim 6 wherein the step of ion implanting impurity determining dopant ions to form spaced apart device regions further comprises the step of forming source and drain regions in the monocrystalline silicon layer proximate the gate electrode.

12. A method for fabricating a semiconductor on insulator (SOI) device having a monocrystalline silicon layer overlying a monocrystalline silicon substrate and separated therefrom by a dielectric layer, the method comprising the steps of:

forming a dielectric isolation region extending through the monocrystalline silicon layer to the dielectric layer;

depositing a gate electrode layer overlying the monocrystalline silicon layer and the dielectric isolation region;

patterning the gate electrode layer to form a P-channel gate electrode and an N-channel gate electrode overlying the monocrystalline silicon layer and a spacer overlying the dielectric isolation region;

etching through the dielectric isolation region and the dielectric layer using the spacer as an etch mask to expose an anode region and a cathode region spaced apart in the monocrystalline silicon substrate;

implanting P-type impurity dopants into the monocrystalline silicon layer to form source and drain regions of a P-channel MOS transistor proximate the P-channel gate electrode and into the anode region in the monocrystalline silicon substrate to form an anode of a substrate diode;

implanting N-type impurity dopants into the monocrystalline silicon layer to form source and drain regions of an N-channel MOS transistor proximate the N-channel gate electrode and into the cathode region in the monocrystalline silicon substrate to form a cathode of a substrate diode;

forming a metal silicide in electrical contact with the anode and the cathode;

depositing an electrically insulating layer overlying the metal silicide;

etching contact openings extending through the electrically insulating layer to expose a portion of the metal silicide; and

forming electrical contacts contacting the anode and the cathode through the contact openings.

13. The method of claim 12 further comprising the step of planarizing the electrically insulating layer.

14. The method of claim 12 wherein the step of forming electrical contacts comprises the step of forming conductive plugs filling the contact openings.

15. The method of claim 12 further comprising the step of ion implanting a well region in the monocrystalline silicon substrate in which the anode and the cathode are formed.

16. The method of claim 12 wherein the step of patterning the gate electrode material comprises the steps of:

patterning the gate electrode material using a photolithographic patterning and etching process to achieve a spacer having a minimum photolithographic feature size; and

subsequently isotropically etching the spacer to reduce the minimum photolithographic feature size.