METHOD OF TRANSMITTING DATA BETWEEN STORAGE VIRTUALIZATION CONTROLLERS AND STORAGE VIRTUALIZATION CONTROLLER DESIGNED TO IMPLEMENT THE METHOD

• US 20060259650A1
• Filed: 05/16/2006
• Published: 11/16/2006
• Est. Priority Date: 05/16/2005
• Status: Active Grant

• Current Assignee: Infortrend Technology Incorporated (Infortrend Corporation)
• Original Assignee: Infortrend Technology Incorporated (Infortrend Corporation)
• Inventors: Chou, Teh-Chern, Huang, Wei-Shun
• Granted Patent: US 7,774,514 B2
• Time in Patent Office: Days
• US Class Current: 710/8
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD

Abstract

A method of transmitting data between storage virtualization controllers (SVCs) in a computer system is disclosed, in which there is an inter-controller communication channel (ICC) between the storage virtualization controllers. The method comprises the steps of: a central processing unit (CPU) of one storage virtualization controller (SVC) sending a data transfer request to an interface that establishes the ICC when the CPU needs to transmit information to the other SVC; and transmitting the information to the other SVC after the interface that establishes the ICC receives the data transfer request, and obtains the information.

Claims

1. A method of transmitting data between storage virtualization controllers in a computer system, the method comprising the steps of:

a central processing unit (CPU) of a first storage virtualization controller (SVC) sending a direct data transfer request to a CPU chipset of the first SVC; and

a first interface in the CPU chipset reading the direct data transfer request, in which the first interface is coupled to a second virtualization controller through a communication channel, and transfers the direct data transfer request to the second virtualization controller via the communication channel, wherein a second interface in the second virtualization controller receives the direct data transfer request.

2. The method of claim 1, wherein the first and the second interfaces are PCI-Express interfaces, the communication channel is a PCI-Express interconnect, and the first and the second interfaces are connected via the PCI-Express interconnect.

3. The method of claim 1, wherein the second interface is located in a second CPU chipset of the second SVC.

4. The method of claim 3, wherein the first and the second interfaces are PCI-Express interfaces, the communication channel is a PCI-Express interconnect, and the first and the second interfaces are connected via the PCI-Express interconnect.

5. The method of any one of claims 1 to 4, wherein the step of the CPU sending the direct data transfer request to the first interface comprises the steps of:

the CPU sending the direct data transfer request to a CPU interface in the CPU chipset;

the CPU interface asserting the direct data transfer request into an internal main bus in the CPU chipset; and

the first interface reading the direct data transfer request.

6. The method of any one of claims 1 to 4, wherein the direct data transfer request comprises a determination message such that the first interface recognizes, through the determination message, that the direct data transfer request is a direct data transfer request, and the first interface reads the direct data transfer request.

7. The method of claim 6, wherein the determination message comprises a virtual address of the direct data transfer request.

8. The method of claim 7, wherein the virtual address is obtained by converting from a destination start address of an access destination.

9. The method of claim 7, wherein the virtual address is obtained by converting from an offset address of the access destination.

10. The method of claim 9, wherein the second storage virtualization controller further comprises the step of:

defining a base address which is defined as a start memory address in the memory of the second storage virtualization controller for the first storage virtualization to access data; and

combining the base address and the offset address to obtain the start address of the access destination.

11. The method of claim 7, further comprising the step of:

the interfaces converting the virtual address into a corresponding physical address.

12. The method of claim 1, wherein the direct data transfer request comprises an data accessing instruction for instructing to perform a read operation or write operation.

13. A storage virtualization controller, comprising:

a CPU;

a memory for storing data; and

a CPU chipset coupled to the CPU and the memory;

wherein the CPU sends a direct data transfer request to another storage virtualization controller via the CPU chipset to directly access data in a second memory of the another storage virtualization.

14. The controller of claim 13, wherein the CPU transmits the direct data transfer request to the another SVC through the CPU chipset, so as to perform direct data access on the second memory of the another storage virtualization through a second CPU chipset of the another SVC.

15. The controller of claim 14, wherein the CPU chipset comprises:

a CPU interface coupled to the CPU for being an interfaces between the CPU and electronic devices in the CPU chipset;

a memory controller coupled to the memory for being an interface between the memory and the electronic devices in the CPU chipset;

a local bus interface for being an interface which communicates with the another storage virtualization controller; and

an internal main bus communicating data signals and control signals between the electronic devices in the CPU chipset;

wherein the direct data access is performed through the local bus interface.

16. The controller of claim 15, wherein the direct data transfer request comprises a determination message such that the local bus interface recognizes, through the determination message, that the direct data transfer request as a direct data transfer request, and the first interface performs the direct data access.

17. The controller of claim 16, wherein the determination message comprises a virtual address of the direct data transfer request.

18. The controller of claim 15, wherein the local bus interface is a PCI-Express interface, and the interface is coupled to the PCI-Express interface of the another SVC via the PCI-Express interconnect.

19. A storage virtualization subsystem, comprising:

a first and a second storage virtualization controllers (SVCs); and

a communication channel provided between the SVCs for exchanging information;

wherein a CPU of the first SVC transmits a direct data transfer request through the communication channel so as to perform direct data access on a memory of the second SVC.

20. The subsystem of claim 19, wherein the first SVC and the second SVC respectively comprise a first and a second CPU chipset, and the first and the second CPU chipsets respectively comprises a first and a second local bus interface which are coupled to the communication channel, and the direct data access is performed by the local bus interfaces.

21. The subsystem of claim 20, wherein the direct data transfer request comprises a determination message such that the local bus interface recognizes, through the determination message, that the direct data transfer request as a direct data transfer request, and the local bus interface performs the direct data access.

22. The subsystem of claim 21, wherein the determination message comprises a virtual address of the direct data transfer request.

23. The subsystem of claim 19, wherein the communication channel between the SVCs is a PCI-Express interconnect.

24. The subsystem of claim 19, further comprising a plurality of physical storage devices coupled to the two storage virtualization controllers to provide data storage space.

25. A storage virtualization computer system, comprising:

a host entity for sending an input/output (F/O) requests;

a first and a second SVCs which are coupled to the host entity for performing operations in response to the I/O requests; and

a communication channel provided between the SVCs for allowing the SVCs to exchange information therebetween; and

a plurality of physical storage devices coupled to the SVCs to provide data storage space for the host entity;

wherein a CPU of the first SVC sends, through the communication channel, a direct data transfer request to the second SVC, to perform direct data access on a memory of the second storage virtualization controller.

26. The computer system of claim 25, wherein the first SVC and the second SVC respectively comprise a first and a second CPU chipset, and the first and the second CPU chipsets respectively comprises a first and a second local bus interface which are coupled to the communication channel, and the direct data access is performed by the local bus interfaces.

27. The computer system of claim 26, wherein the direct data transfer request comprises a determination message such that the local bus interface recognizes, through the determination message, that the direct data transfer request as a direct data transfer request, and the local bus interface performs the direct data access.

28. The computer system of claim 27, wherein the determination message comprises a virtual address of the direct data transfer request.

29. The computer system of claim 25, wherein the communication channel between the SVCs is a PCI-Express interconnect.