Using a processor to program a semiconductor memory

• US 20060259653A1
• Filed: 07/14/2006
• Published: 11/16/2006
• Est. Priority Date: 12/23/2003
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Mueller, Peter D.
• Granted Patent: US 7,594,065 B2
• Time in Patent Office: Days
• US Class Current: 710/8
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators

Abstract

A memory programmer may be coupled through a first processor and a physical interface to a semiconductor memory to be programmed. The interface may be the same interface that allows two separate processors in a multiprocessor memory to communicate with one another in one embodiment. Thus, an independent memory bus coupled directly to the memory components to be programmed may be eliminated, reducing form factor, decreasing costs, and increasing manufacturing throughput in some embodiments of the present invention.

Claims

1. A method comprising:

programming a semiconductor memory by providing the programming data to a processor to provide the data to the semiconductor memory.

2. The method of claim 1 including transferring data from a memory programmer across a physical interface to an integrated circuit including a processor.

3. The method of claim 2 including buffering said programming data on said integrated circuit including said processor.

4. The method of claim 2 including enabling said processor to buffer said programming data.

5. The method of claim 4 including transferring the data to a buffer storage and subsequently transferring the data from said buffer storage to said memory to be programmed.

6. The method of claim 5 including transferring said data from said buffer storage to said memory to be programmed at a slower rate than said data is transferred by said memory programmer to said integrated circuit.

7. The method of claim 5 including transferring the data from a first integrated circuit including said processor to a second integrated circuit including said semiconductor memory to be programmed.

8. The method of claim 5 including transferring the data from the memory programmer to said processor using a board to receive a large number of memories to be programmed, said memories being coupled to processors to receive the data to be programmed.

9. The method of claim 8 including programming the memory after the data has been transferred from said memory programmer and buffered.

10. The method of claim 9 including successively transferring data to a number of memories to be programmed, maintaining power to said memories and programming said memories using said processors after said data has been buffered.

11. A semiconductor memory comprising:

a permanent connection to another integrated circuit including a processor, said connection including a memory bus to couple said processor to said memory.

12. The memory of claim 11 wherein said memory is a flash memory.

13. The memory of claim 11 wherein said memory includes a stack of integrated circuit chips.

14. The memory of claim 13 wherein said chips are packaged in one package including said connection.

15. The memory of claim 14 wherein said package includes no pins to receive a memory bus.

16. A system comprising:

a processor to buffer memory programming data received from a serial link; and

a memory to be programmed by the processor using the programming data.

17. The system of claim 16 wherein said memory is a flash memory.

18. The system of claim 16 wherein said memory includes a stack of integrated circuit chips.

19. The system of claim 16 wherein said memory is packaged separately from said processor and said system including a permanent connection to connect said memory and processor packages.

20. The system of claim 16 wherein said serial link to transfer data at a rate higher than the rate at which said memory may be programmed.

21. The system of claim 18 wherein said processor to store software to buffer data from a memory programmer received at a first rate and to provide said data at a second rate to said memory to be programmed.

22. The system of claim 16 wherein said processor is an application processor.

23. The system of claim 16 wherein said system is a mobile embedded system.