Circuit arrangement and method for secure data processing

• US 20060259851A1
• Filed: 02/15/2006
• Published: 11/16/2006
• Est. Priority Date: 02/15/2005
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Klug, Franz, Sonnekalb, Steffen M.
• Granted Patent: US 7,574,631 B2
• Time in Patent Office: Days
• US Class Current: 714/796
• CPC Class Codes: G06F 21/52 during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow
• CPC Class Codes: G06F 21/77 in smart cards
• CPC Class Codes: G06Q 20/341 Active cards, i.e. cards including their own processing means, e.g. including an IC or chip
• CPC Class Codes: G07F 7/082 Features insuring the integrity of the data on or in the card
• CPC Class Codes: G07F 7/1008 Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system

Abstract

Circuit arrangement for secure data processing for program data with a protected data record. An internal memory provides a protected data record having instruction words and a first check word associated with the instruction words. An arithmetic and logic unit has an input coupled to the internal memory and outputs the first check word from the applied protected data record. A checking apparatus has an input coupled between the internal memory and the arithmetic and logic unit, and allocates a second check word to the instruction words in the protected data record. A comparison apparatus has respective inputs coupled to the checking apparatus and the arithmetic and logic unit, and compares the first check word with the second check word, and outputs an alarm signal when the first check word does not match the second check word.

Claims

1. A circuit arrangement for secure data processing for program data with a protected data record, comprising:

an internal memory which provides a protected data record having instruction words and at least one first check word associated with the instruction words;

an arithmetic and logic unit having an input coupled to the internal memory and which outputs the at least one first check word from the applied protected data record;

a checking apparatus having an input coupled between the internal memory and the arithmetic and logic unit and which allocates at least one second check word to the instruction words in the protected data record; and

a comparison apparatus having respective inputs coupled to the checking apparatus and the arithmetic and logic unit and which compares the at least one first check word with the at least one second check word and outputs an alarm signal when the at least one first check word does not match the at least one second check word.

2. The circuit arrangement of claim 1, further comprising a decoding apparatus coupled between the internal memory and the arithmetic and logic unit and which transforms the instruction words applied to its input.

3. The circuit arrangement of claim 2, wherein the input of the checking apparatus is coupled at least between the decoding apparatus and the arithmetic and logic unit in order to tap off the transformed instruction words and/or is coupled between the internal memory and the decoding apparatus in order to tap off the instruction words, and

wherein the checking apparatus allocates the at least one second check word to the instruction words in the protected data record and/or to the transformed instruction words in the protected data record.

4. The circuit arrangement of claim 1, wherein the allocation of the first and second check words comprises transformation and/or linear superposition of the instruction words in the protected data record.

5. The circuit arrangement of claim 1, wherein the allocation of the second check word depends on a succession of instruction words within the protected data record, which succession is to be processed by the arithmetic and logic unit.

6. The circuit arrangement of claim 5, wherein the succession which is to be processed by the arithmetic and logic unit is dependent on jumps and branches within a series of instruction words in the protected data record.

7. The circuit arrangement of claim 5, wherein the arithmetic and logic unit outputs more than one first check word, and the checking unit compares whether one of the plurality of first check words matches the second check word.

8. The circuit arrangement of claim 1, wherein the allocation of the at least one second check word by the checking apparatus from the protected data record is simulated in software.

9. The circuit arrangement of claim 1, wherein the arithmetic and logic unit processes program data which comprise at least one protected data record.

10. The circuit arrangement of claim 1, further comprising an external memory connected upstream of the internal memory and which stores and provides the program data.

11. The circuit arrangement of claim 10, wherein a cryptographical unit is coupled between the internal memory and the external memory, and the cryptographical unit decrypts program data held in the external memory when the program data are loaded and encrypts the program data when they are stored.

12. The circuit arrangement of claim 1, wherein the circuit arrangement is integrated.

24. The use of the circuit arrangement of claim 1 in a chip card.

13. A method for secure data processing for program data with a protected data record, the method comprising the steps of:

providing a data record which is to be protected and which contains instruction words;

allocating at least one first check word to the instruction words using a first allocation method;

allocating at least one second check word to the instruction words using a second allocation method;

comparing the at least one first check word with the at least one second check word; and

performing an alarm action if the at least one first check word does not match the at least one second check word.

14. The method of claim 13, wherein the step of providing the data record which is to be protected comprises the steps of:

providing program data;

selecting the data record which is to be protected within the program data; and

marking the data record which is to be protected.

15. The method of claim 13, wherein the allocation steps comprise transformation and/or linear superposition of the instruction words in the data record.

16. The method of claim 13, wherein the allocation of the at least one first check word step comprises software-based simulation of the allocation of the at least one second check word step taking place during processing of the instruction words within a circuit arrangement.

17. The method of claim 13, wherein the allocation of the at least one second check word comprises prior transformation of the instruction words, with the second check word being allocated to the data record and/or the transformed data record.

18. The method of claim 13, wherein the allocation of the at least one second check word depends on a succession of instruction words in the protected data record, which succession is to be processed.

19. The method of claim 18, wherein the succession is obtained from a series of instruction words in the protected data record as a result of jumps and branches.

20. The method of claim 13, wherein alternative first check words are obtained from a series of the instruction words in the protected data record as a result of jumps and branches.

21. The method of claim 20, wherein the comparison of the at least one first check word with the at least one second check word also comprises the comparison of the alternative first check words with the at least one second check word.

22. The method of claim 13, wherein the data record to be protected is first divided into small data records which are each allocated at least one first and second check word.

23. The method of claim 22, wherein the data record to be protected is divided at branch and jump points within the data record to be protected.

25. A circuit arrangement for secure data processing for program data with a protected data record, comprising:

an internal memory means for providing a protected data record having instruction words and at least one first check word associated with the instruction words;

an arithmetic and logic means, which has an input coupled to the internal memory, for outputting the at least one first check word from the applied protected data record;

a checking means, which has an input coupled between the internal memory and the arithmetic and logic unit, for allocating at least one second check word to the instruction words in the protected data record; and

a comparing means, which has respective inputs coupled to the checking apparatus and the arithmetic and logic unit, for comparing the at least one first check word with the at least one second check word and for outputting an alarm signal when the at least one first check word does not match the at least one second check word.

26. A computer program having a program code for performing a method for secure data processing for program data with a protected data record, comprising the steps of:

(a) providing a data record which is to be protected and which contains instruction words;

(b) allocating at least one first check word to the instruction words using a first allocation method;

(c) allocating at least one second check word to the instruction words using a second allocation method;

(d) comparing the at least one first check word with the at least one second check word; and

(e) performing an alarm action if the at least one first check word does not match the at least one second check word, when the computer program runs on a computer.