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Method and apparatus for extending processing time in one pipeline stage

  • US 20060259889A1
  • Filed: 04/27/2006
  • Published: 11/16/2006
  • Est. Priority Date: 02/16/1999
  • Status: Active Grant
First Claim
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1. A method of arranging plural circuits, comprising:

  • a) arranging a plurality of substantially similar signal processing circuits together in a predefined pattern so that a signal transfer delay time between each signal processing circuit in the plurality of signal processing circuits is substantially the same; and

    b) providing in ones of said plurality of signal processing circuits;

    one or more signal processing circuits for receiving data signals, one or more circuits for processing the plurality of data signals according to an algorithm, and one or more circuits for receiving the plurality of data signals from an input and for transferring the input data signals to other signal processing circuits for processing therein.

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