SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20060261336A1
• Filed: 05/16/2006
• Published: 11/23/2006
• Est. Priority Date: 05/20/2005
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Sakakura, Masayuki, Nagai, Masaharu, Komori, Shigeki, Osame, Mitsuaki, Ohnuma, Hideto, Yamazaki, Shunpei
• Granted Patent: US 7,579,220 B2
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 27/14623 Optical shielding
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H10K 59/12 Active-matrix OLED [AMOLED] displays

Abstract

It is an object of the present invention to form a plurality of elements in a limited area to reduce the area occupied by the elements for integration so that further higher resolution (increase in number of pixels), reduction of each display pixel pitch with miniaturization, and integration of a driver circuit that drives a pixel portion can be advanced in semiconductor devices such as liquid crystal display devices and light-emitting devices that has EL elements. A photomask or a reticle provided with an assist pattern that is composed of a diffraction grating pattern or a semi-transparent film and has a function of reducing a light intensity is applied to a photolithography process for forming a gate electrode to form a complicated gate electrode. In addition, a top-gate TFT that has the multi-gate structure described above and a top gate TFT that has a single-gate structure can be formed on the same substrate just by changing the mask without increasing the number of processes.

Claims

1. A semiconductor device comprising:

a semiconductor layer having a source region, a drain region, a first channel forming region and a second channel forming region between the source region and the drain region, and an intermediate impurity region between the first channel forming region and the second channel forming region;

a gate insulating layer above the semiconductor layer; and

a gate electrode comprising a first conductive layer, a second conductive layer in contact with the first conductive layer and a third conductive layer in contact with the first conductive layer on the gate insulating layer,

wherein the first conductive layer is overlapped with at least the first channel forming region, the intermediate impurity region, and the second channel forming region,

wherein the second conductive layer is overlapping the first channel forming region, and

wherein the third conductive layer is located apart from the second conductive layer, and is overlapping the second channel forming region.

2. The semiconductor device according to claim 1, wherein the second conductive layer and the third conductive layer are formed of the same material.

3. The semiconductor device according to claim 1, wherein the first conductive layer and the second conductive layer are formed of different materials.

4. The semiconductor device according to claim 1, wherein the first conductive layer has a width that is larger than a value obtained by adding a width of the first channel forming region, a width of the second channel forming region, and a width of the intermediate impurity region.

5. The semiconductor device according to claim 1, wherein the width of the second conductive layer is equal to the width of the first channel forming region.

6. The semiconductor device according to claim 1, wherein the width of the third conductive layer is equal to the width of the second channel forming region.

7. The semiconductor device according to claim 1, wherein the film thickness of the first conductive layer is thinner than the second conductive layer or the third conductive layer.

8. The semiconductor device according to claim 1, wherein the source region and the drain region are located outside the first conductive layer.

9. A semiconductor device comprising:

a semiconductor layer-having a pair of higher concentration impurity regions, a first channel forming region and a second channel forming region between the pair of higher concentration impurity regions, a first lower concentration impurity region between one of the pair of higher concentration impurity regions and the first channel forming region, a second lower concentration impurity region between the other of the pair of higher concentration impurity regions and the second channel forming region, and an intermediate impurity region between the first channel forming region and the second channel forming region;

a gate insulating layer above the semiconductor layer; and

a gate electrode comprising a first conductive layer, a second conductive layer in contact with the first conductive layer and a third conductive layer in contact with the first conductive layer on the gate insulating layer,

wherein the first conductive layer is overlapping at least the first lower concentration impurity region, the first channel forming region, the intermediate impurity region, the second lower concentration impurity region, and the second channel forming region,

wherein the second conductive layer is overlapping the first channel forming region, and

wherein the third conductive layer is located apart from the second conductive layer, and is overlapping the second channel forming region.

10. The semiconductor device according to claim 9, wherein the first lower concentration impurity region and the second lower concentration impurity region include the same concentration of n-type or p-type impurity element.

11. The semiconductor device according to claim 9, wherein the intermediate impurity region includes the same concentration of n-type or p-type impurity element as that of the first lower concentration impurity region or the second lower concentration impurity region.

12. The semiconductor device according to claim 9, wherein the width of the first lower concentration impurity region is equal to the width of the second lower concentration impurity region.

13. The semiconductor device according to claim 9, wherein the second conductive layer and the third conductive layer are formed of the same material.

14. The semiconductor device according to claim 9, wherein the first conductive layer and the second conductive layer are formed of different materials.

15. The semiconductor device according to claim 9, wherein the first conductive layer has a width obtained by adding a width of the first channel forming region, a width of the second channel forming region, a width of the intermediate impurity region, a width of the first lower concentration impurity region, and a width of the second lower concentration impurity region.

16. The semiconductor device according to claim 9, wherein the width of the second conductive layer is equal to the width of the first channel forming region.

17. The semiconductor device according to claim 9, wherein the width of the third conductive layer is equal to the width of the second channel forming region.

18. The semiconductor device according to claim 9, wherein the film thickness of the first conductive layer is thinner than the second conductive layer or the third conductive layer.

19. The semiconductor device according to claim 9, wherein the pair of higher concentration impurity regions is located outside the first conductive layer.

20. A method for manufacturing a semiconductor device comprising the steps of:

forming an insulating film on a semiconductor layer;

forming a first conductive film on the insulating film;

forming a second conductive film on the first conductive film;

forming a resist pattern on the second conductive film having thin end portions and a thin central portion;

etching the second conductive film and the first conductive film to form a first conductive layer from the first conductive film and a second conductive layer and a third conductive layer that are located apart from each other on the first conductive layer from the first conductive film;

doping the semiconductor layer with an impurity element by using the first conductive layer, the second conductive layer, and the third conductive layer as masks to form a pair of higher concentration impurity regions in the semiconductor layer located outside the first conductive layer; and

doping the semiconductor layer with an impurity element by using the second conductive layer and the third conductive layer as masks to form a lower concentration impurity regions in the semiconductor layer overlapped with the first conductive layer.

21. The method for manufacturing the semiconductor device according to claim 20, wherein the first conductive layer is formed by etching the first conductive film, and the second conductive layer and the third conductive layer are formed by etching the second conductive film.

22. The method for manufacturing the semiconductor device according to claim 20, wherein the width of the first conductive layer is wider than the sum of the width of the second conductive layer and the width of the third conductive layer.

23. The method for manufacturing the semiconductor device according to claim 20, wherein the resist pattern is formed by using a photomask or a reticle that has a diffraction grating pattern or a semi-transparent film.

24. The method for manufacturing the semiconductor device according to claim 20, wherein the first conductive layer, the second conductive layer, and the third conductive layer serve as a gate electrode.

25. A method for manufacturing a semiconductor device comprising the steps of:

forming an insulating film covering a semiconductor layer;

laminating a first conductive film, a second conductive film, and a third conductive film on the insulating film;

forming a resist pattern that is partially different in film thickness on the third conductive film;

etching the third conductive film, the second conductive film, and the first conductive film to form an electrode that has a portion where the first conductive film, the second conductive film, and the third conductive film are laminated and a portion of a single layer of the first conductive film; and

forming a transparent conductive film on the insulating film in contact with an upper surface of the portion of the single layer of the first conductive layer.

26. The method for manufacturing the semiconductor device according to claim 25, wherein the resist pattern is formed by using a photomask or a reticle that has a diffraction grating pattern or a semi-transparent film.

27. The method for manufacturing the semiconductor device according to claim 25, wherein the resist pattern has a site with a first film thickness and a site with a second film thickness thinner than the first film thickness, and the site that has the second film thickness is an end portion of the resist pattern.

28. The method for manufacturing the semiconductor device according to claim 25, wherein the first conductive layer is contact with a portion of the semiconductor layer through a contact hole formed in the insulating film.

29. The method for manufacturing the semiconductor device according to claim 25, wherein the first conductive film is formed of a high melting point metal element or a high melting point metal compound.

30. The method for manufacturing the semiconductor device according to claim 25, wherein the second conductive film is formed of an aluminum element or an aluminum alloy.

31. The method for manufacturing the semiconductor device according to claim 25, wherein the third conductive film is formed of a high melting point metal element or a high melting point metal compound.