High voltage silicon carbide devices having bi-directional blocking capabilities and methods of fabricating the same
First Claim
16. A silicon carbide (SiC) thyristor, comprising:
- a first SiC layer having a first conductivity type on a first surface of a voltage blocking SiC substrate having a second conductivity type;
a first SiC anode region on the first SiC layer and having the second conductivity type;
a first SiC gate region in the first SiC layer, having the first conductivity type and being adjacent to the first SiC anode region;
a second SiC layer having the first conductivity type on a second surface of the voltage blocking SiC substrate;
a second SiC anode region on the second SiC layer and having the second conductivity type;
a second SiC gate region in the second SiC layer, having the first conductivity type and being adjacent to the second SiC anode region; and
first, second, third and fourth contacts on the first and second SiC anode regions and on the first and second SiC gate regions, respectively.
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Abstract
High voltage silicon carbide (SiC) devices, for example, thyristors, are provided. A first SiC layer having a first conductivity type is provided on a first surface of a voltage blocking SiC substrate having a second conductivity type. A first region of SiC is provided on the first SiC layer and has the second conductivity type. A second region of SiC is provided in the first SiC layer. The second region of SiC has the first conductivity type and is adjacent to the first region of SiC. A second SiC layer having the first conductivity type is provided on a second surface, opposite the first surface, of the voltage blocking SiC substrate. First, second and third contacts are provided on the first region of SiC, the second region of SiC and the second SiC layer, respectively. Related methods of fabricating high voltage SiC devices are also provided.
83 Citations
42 Claims
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16. A silicon carbide (SiC) thyristor, comprising:
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a first SiC layer having a first conductivity type on a first surface of a voltage blocking SiC substrate having a second conductivity type;
a first SiC anode region on the first SiC layer and having the second conductivity type;
a first SiC gate region in the first SiC layer, having the first conductivity type and being adjacent to the first SiC anode region;
a second SiC layer having the first conductivity type on a second surface of the voltage blocking SiC substrate;
a second SiC anode region on the second SiC layer and having the second conductivity type;
a second SiC gate region in the second SiC layer, having the first conductivity type and being adjacent to the second SiC anode region; and
first, second, third and fourth contacts on the first and second SiC anode regions and on the first and second SiC gate regions, respectively. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23)
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24. A method of forming a high voltage silicon carbide (SiC) device, comprising:
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forming a first SiC layer having a first conductivity type on a first surface of a voltage blocking SiC substrate having a second conductivity type;
forming a first region of SiC on the first SiC layer and having the second conductivity type;
forming a second region of SiC in the first SiC layer, having the first conductivity type and being adjacent to the first region of SiC;
forming a second SiC layer having the first conductivity type on a second surface of the voltage blocking SiC substrate;
forming a third region of SiC on the second SiC layer and having the second conductivity type;
forming a fourth region of SiC in the second SiC layer, having the first conductivity type and being adjacent to the third region of SiC; and
forming first and second contacts on the first and third regions of SiC, respectively. - View Dependent Claims (1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 25, 26, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39)
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26-1. The method of claim 24, further comprising performing a bevel edge termination process on sidewalls of the SiC device.
- 28. The method of claim 27, wherein the bevel edge termination process comprises one of plasma etching and mechanical grinding.
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40. A high voltage silicon carbide (SiC) device, comprising:
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a first SiC layer having a first conductivity type on a first surface of a voltage blocking SiC epilayer having a second conductivity type;
a first region of SiC on the first SiC layer and having the second conductivity type;
a second region of SiC in the first SiC layer, having the first conductivity type and being adjacent to the first region of SiC;
a second SiC layer having the first conductivity type on a second surface of the voltage blocking SiC epilayer;
a third region of SiC on the second SiC layer and having the second conductivity type;
a fourth region of SiC in the second SiC layer, having the first conductivity type and being adjacent to the third region of SiC; and
first and second contacts on the first and third regions of SiC, respectively.
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41. A silicon carbide (SiC) thyristor, comprising:
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a first SiC layer having a first conductivity type on a first surface of a voltage blocking SiC epilayer having a second conductivity type;
a first SiC anode region on the first SiC layer and having the second conductivity type;
a first SiC gate region in the first SiC layer, having the first conductivity type and being adjacent to the first SiC anode region;
a second SiC layer having the first conductivity type on a second surface of the voltage blocking SiC epilayer;
a second SiC anode region on the second SiC layer and having the second conductivity type;
a second SiC gate region in the second SiC layer, having the first conductivity type and being adjacent to the second SiC anode region; and
first, second, third and fourth contacts on the first and second SiC anode regions and on the first and second SiC gate regions, respectively.
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42. A method of forming a high voltage silicon carbide (SiC) device, comprising:
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forming a first SiC layer having a first conductivity type on a first surface of a voltage blocking SiC epilayer having a second conductivity type;
forming a first region of SiC on the first SiC layer and having the second conductivity type;
forming a second region of SiC in the first SiC layer, having the first conductivity type and being adjacent to the first region of SiC;
forming a second SiC layer having the first conductivity type on a second surface of the voltage blocking SiC epilayer;
forming a third region of SiC on the second SiC layer and having the second conductivity type;
forming a fourth region of SiC in the second SiC layer, having the first conductivity type and being adjacent to the third region of SiC; and
forming first and second contacts on the first and third regions of SiC, respectively.
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Specification