Memory utilizing oxide-nitride nanolaminates

• US 20060261376A1
• Filed: 07/25/2006
• Published: 11/23/2006
• Est. Priority Date: 07/08/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ahn, Kie Y., Forbes, Leonard
• Granted Patent: US 7,494,873 B2
• Time in Patent Office: Days
• US Class Current: 257/216
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Structures, systems and methods for transistors utilizing oxide-nitride nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate insulator includes oxide-nitride nanolaminate layers to trap charge in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers.

Claims

1. A method for forming a memory array, comprising:

forming a number of vertical pillars in rows and columns extending outwardly from a substrate and separated by a number of trenches, wherein the number of vertical pillars serve as transistors including a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator in the trenches along rows of pillars, wherein along columns of the pillars adjacent pillars include a first transistor on one side of a trench and a second transistor which operates as a reference cell on the opposite side of the trench, and wherein forming the gate insulator includes atomic layer depositing a storage layer within silicon dioxide as part of a nanolaminate;

forming a number of bit lines coupled to the second source/drain region of each transistor along rows of the memory array;

forming a number of word lines coupled to the gate of each transistor along columns of the memory array;

forming a number of sourcelines in a bottom of the trenches between rows of the pillars and coupled to the first source/drain regions of each transistor along rows of pillars, wherein along columns of the pillars the first source/drain region of each transistor in column adjacent pillars couple to the sourceline in a shared trench such that the first transistor and the second transistor share a common sourceline; and

wherein the number of vertical pillars can be programmed in a reverse direction to have a charge trapped in the gate insulator adjacent to the first source/drain region by biasing a sourceline to a voltage higher than VDD, grounding a bitline, and selecting a gate by a wordline address.

2. The method of claim 1, wherein forming a number of sourcelines in a bottom of the trenches between rows of the pillars includes implanting a doped region in the bottom of the trench.

3. The method of claim 1, wherein forming a gate insulator above the channel region in the trenches along rows of pillars includes forming a gate insulator having a thickness less than or equal to 10 nanometers (nm).

4. The method of claim 1, wherein atomic layer depositing a storage layer includes atomic layer depositing silicon nitride.

5. The method of claim 1, wherein atomic layer depositing a storage layer includes atomic layer depositing aluminum nitride.

6. The method of claim 1, wherein atomic layer depositing a storage layer includes atomic layer depositing gallium nitride.

7. The method of claim 1, wherein atomic layer depositing a storage layer includes atomic layer depositing gallium aluminum nitride.

8. The method of claim 1, wherein atomic layer depositing a storage layer includes atomic layer depositing tantalum aluminum nitride.

9. The method of claim 1, wherein atomic layer depositing a storage layer includes atomic layer depositing titanium silicon nitride.

10. The method of claim 1, wherein atomic layer depositing a storage layer includes atomic layer depositing titanium aluminum nitride.

11. The method of claim 1, wherein atomic layer depositing a storage layer includes atomic layer depositing tungsten aluminum nitride.

12. A method of forming a memory array, comprising:

forming a number of vertical pillars in a semiconductor substrate, the vertical pillars separated by trenches;

forming a pair of vertical transistors on opposing sides of the trench, wherein forming a transistor includes;

forming a first source/drain region adjacent to a bottom of a pillar;

forming a second source/drain region adjacent to a top of the pillar;

forming a nanolaminate insulator over a channel region on a wall of the pillar between the first source/drain region and the second source/drain region, the nanolaminate insulator including a storage layer formed by atomic layer deposition techniques;

forming a gate over the nanolaminate insulator layer;

coupling circuitry to the pair of vertical transistors wherein the circuitry is operable to program a first transistor in a first direction, and read the first transistor in a second direction opposite from the first direction.

13. The method of claim 12, wherein coupling circuitry to the pair of vertical transistors includes coupling circuitry to compare electrical characteristics in a channel region of the first transistor with electrical characteristics of a channel in a second transistor of the pair as a reference transistor.

14. The method of claim 13, wherein comparing electrical characteristics includes comparing source/drain current.

15. The method of claim 12, wherein forming a nanolaminate insulator includes forming a storage layer having a thickness less than or equal to 10 nanometers.

16. The method of claim 15, wherein forming a nanolaminate insulator includes forming a storage layer having a thickness approximately equal to 4 nanometers.

17. A method of forming a memory array, comprising:

forming a number of vertical pillars in a semiconductor substrate, the vertical pillars separated by trenches;

forming a pair of vertical transistors on opposing sides of the trench, wherein forming a transistor includes;

forming a first source/drain region adjacent to a bottom of a pillar;

forming a second source/drain region adjacent to a top of the pillar;

forming a nanolaminate insulator over a channel region on a wall of the pillar between the first source/drain region and the second source/drain region, the nanolaminate insulator including a storage layer formed by atomic layer deposition techniques;

forming a gate within the trench that serves as a common gate between transistors on the opposing sides of the trench;

coupling circuitry to the pair of vertical transistors wherein the circuitry is operable to program a first transistor in a first direction, and read the first transistor in a second direction opposite from the first direction.

18. The method of claim 17, further including forming a sourceline in a base of the trench wherein the sourceline is common to transistors on opposing sides of the trench.

19. The method of claim 18, wherein forming a sourceline in the base of the trench includes implanting a dopant into a base of the trench to form a conductive source line.

20. The method of claim 17, wherein coupling circuitry to the pair of vertical transistors includes coupling circuitry to compare electrical characteristics in a channel region of the first transistor with electrical characteristics of a channel in a second transistor of the pair as a reference transistor.

21. The method of claim 17, wherein the storage layer includes a nitride layer.

22. The method of claim 17, wherein forming a storage layer by atomic layer deposition techniques includes forming a storage layer with an electron affinity less than 4.1 eV providing a positive conduction band offset with silicon oxide.