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Memory utilizing oxide-nitride nanolaminates

  • US 20060261376A1
  • Filed: 07/25/2006
  • Published: 11/23/2006
  • Est. Priority Date: 07/08/2002
  • Status: Active Grant
First Claim
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1. A method for forming a memory array, comprising:

  • forming a number of vertical pillars in rows and columns extending outwardly from a substrate and separated by a number of trenches, wherein the number of vertical pillars serve as transistors including a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator in the trenches along rows of pillars, wherein along columns of the pillars adjacent pillars include a first transistor on one side of a trench and a second transistor which operates as a reference cell on the opposite side of the trench, and wherein forming the gate insulator includes atomic layer depositing a storage layer within silicon dioxide as part of a nanolaminate;

    forming a number of bit lines coupled to the second source/drain region of each transistor along rows of the memory array;

    forming a number of word lines coupled to the gate of each transistor along columns of the memory array;

    forming a number of sourcelines in a bottom of the trenches between rows of the pillars and coupled to the first source/drain regions of each transistor along rows of pillars, wherein along columns of the pillars the first source/drain region of each transistor in column adjacent pillars couple to the sourceline in a shared trench such that the first transistor and the second transistor share a common sourceline; and

    wherein the number of vertical pillars can be programmed in a reverse direction to have a charge trapped in the gate insulator adjacent to the first source/drain region by biasing a sourceline to a voltage higher than VDD, grounding a bitline, and selecting a gate by a wordline address.

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