Vertical integrated-gate CMOS device and its fabrication process

• US 20060261406A1
• Filed: 05/18/2005
• Published: 11/23/2006
• Est. Priority Date: 05/18/2005
• Status: Abandoned Application

• Current Assignee: Yijian Chen
• Original Assignee: Yijian Chen
• Inventors: Chen, Yijian
• Application Number:
  US11/130,564
• Publication Number:
  US 20060261406A1
• Time in Patent Office: Days
• US Class Current: 257/329
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/78642 Vertical transistors

Abstract

A vertical integrated-gate CMOS (Complementary Metal-Oxide-Silicon field effect transistor) device is invented for the first time and its possible fabrication processes are proposed. This CMOS architecture integrates PMOS (P-channel MOSFET) and NMOS (N-channel MOSFET) together vertically to increase the transistor density, and use epitaxy layer thickness to define the transistor channel/gate length. The epitaxy growth rate can be controlled accurately thus with much less channel/gate critical dimension (CD) variations than defined by lithography, which also relaxes lithographic resolution requirements for continuous cost-effective CMOS shrinking. This device structure can be used in the post-planar-CMOS ultra-dense integrated circuits.

Claims

1. Yijian Chen claims that he invents the vertical integrated-gate CMOS device as shown in the FIG. 2 of the attached document, and he designs several examples of process sequence as shown in FIGS. 3, 4, 5 and 6 of the attached document to fabricate this device.

1-1. Yijian Chen claims that he invents the vertical integrated-gate CMOS device as shown in the FIG. 2 of the attached document, and he designs several examples of process sequence as shown in FIGS. 3, 4, 5 and 6 of the attached document to fabricate this device.