Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peeling

• US 20060261490A1
• Filed: 07/28/2006
• Published: 11/23/2006
• Est. Priority Date: 04/15/2003
• Status: Active Grant

• Current Assignee: Chao-Yuan Su, Chender Huang, Chenming Hu, Hao-Yi Tsai, Hsin-Hui Lee, Pei-Haw Tsao, Shang Y. Hou, Shin Puu Jeng
• Original Assignee: Chao-Yuan Su, Chender Huang, Chenming Hu, Hao-Yi Tsai, Hsin-Hui Lee, Pei-Haw Tsao, Shang Y. Hou, Shin Puu Jeng
• Inventors: Lee, Hsin-Hui, Su, Chao-Yuan, Hu, Chenming, Tsai, Hao-Yi, Tsao, Pei-Haw, Huang, Chender, Jeng, Shin Puu, Hou, Shang Y.
• Granted Patent: US 7,294,937 B2
• Time in Patent Office: Days
• US Class Current: 257/775
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A multi-layered semiconductor structure with free areas limiting the placement of test keys. First and second scribe lines intersect to define one corner point of a die. The first and second scribe lines are part of the multilayered structure and at least one layer of the multi-layer structure is a low-k dielectric layer. Free area A₁ is defined on the first scribe line and is defined by the equation A₁=D₁×S₁, where D₁ is the distance from the corner point of the die toward the main area of the die, and S₁ is the width of the first scribe line. Free area A_S is defined at the intersection of the first scribe line and the second scribe line adjacent the die and is defined by the equation A_S=S₁×S₂, where S₂ is the width of the second scribe line.

Claims

1. A multi-layer semiconductor wafer structure defining a multiplicity of dies formed thereon, said wafer structure comprising:

at least two first scribe lines having a selected width S₁, each of said at least two first scribe lines extending along a first orientation and defining a first edge of at least two first dies of said multiplicity of dies;

at least two second scribe lines having a selected width S₂, each of said at least two second scribe lines extending along a second orientation and defining a second edge of at least two second dies and intersecting said at least two first scribe lines, and said first edges of said at least two first dies and said second edges of said at least two second dies intersecting at corner points;

first restricted areas A₁ defined on said first scribe line where placement of a test key is restricted, and said first restricted areas A₁ being defined by the equation A₁=D₁×

S₁, where D₁ is the distance along the first edge extending from a corner point of said at least two first dies;

second restricted areas A_S at intersections of said at least two first scribe lines and said at least two second scribe lines, said second restricted areas A_S being defined by the equation A_S=S₁×

S₂;

at least one first test key formed on each one of said at least two first and said at least two second scribe lines, but not on said restricted areas A and A_S; and

at least one second test key formed in at least one of said A₁ restricted areas and said A_S restricted areas.

2. The multi-layer semiconductor wafer structure of claim 1 wherein at least one layer of said wafer structure is a low-k dielectric layer.

3. (The multi-layer semiconductor wafer structure of claim 2 wherein the low-k dielectric layer has a dielectric constant of less than approximately 3.5.

4. (The multi-layer semiconductor wafer structure of claim 3 wherein the low-k dielectric layer has a dielectric constant of less than 3.0.

5. The multi-layer semiconductor wafer structure of claim 2 wherein the low-k dielectric layer is a material selected from the group consisting of CVD-SiOC, SiOCN, Spin-on SiOC, CVD deposited polymer, Spin-on polymer, FSG, SiO₂ and combinations thereof.

6. The multi-layer semiconductor wafer structure of claim 1 wherein the free areas are defined on the top layer of the multi-layer structure.

7. The multi-layer semiconductor wafer structure of claim 1 wherein the free areas are defined on at least one of the top three layers of the multi-layer structure.

8. The multi-layer semiconductor wafer structure of claim 1 wherein said at least one second test key is formed in one of said first restricted areas, said at least one second test key having a measurement ratio R₁, wherein the measurement ratio is defined by the equation:

R₁=M₁/A₁, wherein M₁ is the total area of said at least one second test key formed on the first restricted area A₁, and R₁ is less than about 10%.

9. The multi-layer semiconductor wafer structure of claim 1 wherein the distance D₁ is less than about 600 μ

m.

10. The multi-layer semiconductor wafer structure of claim 1 wherein the width S₁ of the first scribe line is greater than about 20 μ

m.

11. The multi-layer semiconductor wafer structure of claim 1 wherein the multi-layer structure is formed on a substrate selected from the group consisting of bulk S₁, SOI, SiGe, GaAs, InP, and a combination thereof.

12. The multi-layer semiconductor wafer structure of claim 1 wherein said first die comprises:

a first peripheral region inside of and extending parallel to said first scribe line;

a second peripheral region inside of and extending parallel to said second scribe line and intersecting said first peripheral region to form a corner area;

a conductive ring formed between said first die and said first peripheral region and said second peripheral region; and

an array of apertures formed in the conductive ring and adjacent the corner area of the first die.

13. The multi-layer semiconductor wafer structure of claim 12 wherein said array of apertures comprises at least two slots.

14. The multi-layer semiconductor wafer structure of claim 12 wherein said array of apertures comprises two rows of holes.

15. The multi-layer semiconductor wafer structure of claim 12 wherein the array of apertures extends along at least one of the first peripheral region and the second peripheral region.

16. The multi-layer semiconductor wafer structure of claim 12 wherein the first die further comprises a circuit area with a plurality of circuit elements, wherein the conductive ring is electrically connected to the circuit elements to apply one of a power source and a ground potential to the circuit elements.

17. The multi-layer semiconductor wafer structure of claim 12 wherein the conductive ring has a width of between 501 μ

m and about 300 μ

m.

18. The multi-layer semiconductor wafer structure of claim 1 wherein said at least one second test key is formed in one of said second restricted areas A_S, said second test key having a measurement ratio R_S that is less than 10% and is defined by the equation R_S=M_S/A_S, wherein M_S is the total area of said at least one second test key formed on the second restricted area A_S.

19. The multi-layer semiconductor wafer structure of claim 1 wherein the width of the scribe lines S₁ and S₂ is greater than about 20 μ

m.

20. The multi-layer semiconductor wafer structure of claim 1 wherein said at lest one first restricted area comprises a first free area A₁ on the first scribe line and another first free area A₂ on the second scribe line, said second free area defined by the equation A₂=D₂×

S₂ where D₂ is the distance along the second edge extending from the corner point of the first die and S₂ is the width of the second scribe line.

21. The multi-layer semiconductor wafer structure of claim 20 further comprising:

at least one test key formed on at least one of the free areas A₁, A₂ and A_S;

wherein a first measurement ratio R₁ is defined as the equation R₁=M₁/A₁, wherein M₁ is the total area of the test keys formed on the first free area A₁;

wherein a second measurement ratio R₂ is defined as the equation R₂=M₂/A₂, wherein M₂ is the total area of the test keys formed on the second free area A₂;

wherein a third measurement ratio R_S is defined as the equation R_S=M_S/A_S, wherein M_S is the total area of the test keys formed on the third area A_S; and

wherein a total measurement ratio R is defined as the equation R=(M₁+M₂+M_S)/(A₁+A₂+A_S).

22. The multi-layer semiconductor wafer structure of claim 21 wherein R₁ is less than about 10%.

23. The multi-layer semiconductor wafer structure of claim 21 wherein R₂ is less than about 10%.

24. The multi-layer semiconductor wafer structure of claim 21 wherein R_S is less than about 10%.

25. The multi-layer semiconductor wafer structure of claim 21 wherein the ratio R is less than about 10%.

26. The multi-layer semiconductor wafer structure of claim 20 wherein the first distance D₁ is less than about 600 μ

m.

27. The multi-layer semiconductor wafer structure of claim 20 wherein the distance D₂ along the second direction is less than about 600 μ

m.

28. The multi-layer semiconductor wafer structure of claim 20 wherein the width S₁ of the first scribe line is greater than about 201 μ

m.

29. The multi-layer semiconductor wafer structure of claim 20 wherein the width S₂ of the second scribe line is greater than about 20 μ

m.

30. The multilayer semiconductor wafer structure of claim 8 wherein at least another second test key is formed on said second restricted area A_S, said at least another second test key having a measurement ratio R_S that is less than 10%, said measurement ration R_S defined by the equation R_S=M_S/A_S, wherein M_S is the total area of said at least another second test key formed on said second restricted area A_S.