Arrangement and method for monitoring and controlling a plurality of series-connected capacitors

• US 20060261784A1
• Filed: 05/19/2006
• Published: 11/23/2006
• Est. Priority Date: 05/21/2005
• Status: Active Grant

• Current Assignee: Diehl Luftfahrt Electronik GmbH
• Original Assignee: Diehl Luftfahrt Electronik GmbH
• Inventors: Kolb, Tobias, Jordan, Jens
• Granted Patent: US 7,671,569 B2
• Time in Patent Office: Days
• US Class Current: 320/166
• CPC Class Codes: H01G 11/10 Multiple hybrid or EDL capacitors, e.g. arrays or modules housings, cases, encapsulations or mountings thereof H01G11/78
• CPC Class Codes: H01G 11/14 Arrangements or processes for adjusting or protecting hybrid or EDL capacitors emergency protective circuit arrangements specially adapted for capacitors, and effecting automatic switching in the event of an undesired change from normal working conditions H02H7/16; emergency protective circuit arrangements for limiting excess current or voltages without disconnection H02H9/00
• CPC Class Codes: H02J 7/0016 using shunting, discharge or bypass circuits
• CPC Class Codes: Y02E 60/13 Energy storage using capacitors

Abstract

A method for monitoring and controlling a plurality of series-connected capacitance, wherein at least during the discharge of the capacitances, there is determined a voltage of every capacitance, and in the instance of a drop-off of a voltage of one of the capacitances below a first threshold voltage of this capacitance, the capacitance is bridged over to at least the end of the discharge. Also provided are devices for determining every voltage of every capacitance, devices for symmetrizing voltages among the capacitances, and devices for the deactivation of at least one of the capacitances.

Claims

1. A method for monitoring and controlling a plurality of series-connected capacitances, comprising:

determining a voltage of every capacitance at least during a discharge of said capacitances; and

in an instance of a drop-off of the voltage of one of the capacitances below a first threshold voltage, said capacitance is bridged over to at least the end of the discharge.

2. A method according to claim 1, wherein a switch implements the bridging over of said capacitances.

3. A method according to claim 1, wherein for effectuating a symmetrizing of the voltages of the capacitors, at least during a charging of said capacitances there is determined the voltage of every capacitance;

and in an instance of a drop-off of a voltage of one of the capacitances below a second threshold voltage, the capacitance with the highest voltage has a resistance R connected in parallel therewith.

4. A method according to claim 3, wherein in the instance of an exceeding of the voltage of one of the capacitances above a third threshold voltage, said capacitances have a resistance R connected in parallel therewith.

5. A method according to claim 4, wherein the second threshold voltage and/or the third threshold voltage are determined in dependence upon the voltages of all of said capacitances.

6. A method according to claim 5, wherein said threshold voltages are determined in dependence upon the sum of the voltages of all of said capacitances.

7. An arrangement including a plurality of series-connected capacitances and a switching circuit, comprising:

means (21, 121, 110) for determining every voltage of every capacitance;

means (150, 52, 71, M_S) for symmetrizing of the voltages of the capacitances among each other; and

means (150, 51, 61 M_B) for the deactivation of at least one of the capacitances.

8. An arrangement according to claim 7, wherein said means for deactivation includes a deactivating switch (M_B) which bridges over an applicable capacitance for the deactivation thereof.

9. An arrangement according to claim 8, wherein said deactivation switch comprises at least one semiconductor component having a source connection and a drain connection each directly connection with respectively one terminal of the capacitance.

10. An arrangement according to claim 9, wherein the semiconductor component comprises a field-effect transistor (M_B).

11. An arrangement according to claim 7, wherein said means for deactivation includes a level transducer (51).

12. An arrangement according to claim 7, wherein said means for symmetrizing includes a resistance (R) and a symmetrizing switch (M_S) which is connected in series with the resistance (R), and which is connected in parallel with the applicable capacitance for symmetrizing thereof.

13. An arrangement according to claim 12, wherein the symmetrizing switch comprises at least one semiconductor component having a source connection and a drain connection which selectively are directly connected with the resistance (R).

14. An arrangement according to claim 13, wherein said at least one semiconductor component comprises a field-effect transistor (M_S).

15. An arrangement according to claim 7, wherein the means for symmetrizing comprises a level transducer (52).

16. An arrangement according claim 11 or claim 15, wherein said switching circuit comprises an integrated control circuit, such as a microcontroller (100), wherein one or more outputs of said integrated control circuit are multiplexable through a multiplexer (150) at every level transducer (51, 52), having one said capacitance associated therewith.

17. An arrangement according to claim 7, wherein the means (21) for determining the voltage comprises a differential amplifier having two outlets which are connected with the terminals of the applicable capacitances.

18. An arrangement according to claim 16, wherein one or more outputs of every said means (21) for determining the voltage at one or more inputs of the integrated control circuit (100) are multiplexable through a multiplexer (121).

19. An arrangement according to claim 7, wherein every capacitance comprises a plurality of condensers (C), which are connected in parallel.

20. An arrangement according to claim 19, wherein said condensers (C) form a condenser matrix (10).