Voltage conversion circuit with stable transition delay characteristic

• US 20060261851A1
• Filed: 05/05/2006
• Published: 11/23/2006
• Est. Priority Date: 05/20/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Min-Su
• Granted Patent: US 7,355,446 B2
• Time in Patent Office: Days
• US Class Current: 326/81
• CPC Class Codes: H03K 19/00323 Delay compensation
• CPC Class Codes: H03K 3/011 Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature to maintain energy constant H03K3/015
• CPC Class Codes: H03K 3/0375 provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit

Abstract

A voltage conversion circuit changes an input signal of a first voltage into an output signal of a second voltage. The circuit includes an input terminal receiving an input signal, an output terminal generating an output signal, and first and second level-shifting units connected in parallel between the input and output terminals. The first and second level-shifting units have different transition delay characteristics, enabling rising and falling transition delays to be variable in the same ratio when the first and second voltages are changed.

Claims

1. A voltage conversion circuit, comprising:

an input terminal receiving an input signal of a first voltage;

an output terminal generating an output signal of a second voltage; and

first and second level-shifting units connected between the input and output terminals,

wherein the first and second level-shifting units have different transition delay characteristics from each other so that rising and falling transition delays of the output signal are varied in the same rate when the first and second voltages are changed.

2. The voltage conversion circuit as set forth in claim 1, wherein each of the first and second level-shifting units has three signal transmission stages.

3. The voltage conversion circuit as set forth in claim 1, wherein when the first voltage is higher than the second voltage and the input signal goes to high level from low level, the signal transmission stages of the first level-shifting unit operate in a transition delay characteristic of ‘

FFF’ and

the signal transmission stages of the second level-shifting unit operate in a transition delay characteristic of ‘

FSS’

,

wherein the ‘

F’

represents a fast transition delay of a MOS transistor based on a gate-source voltage and the ‘

S’

represents a slow transition delay of a MOS transistor based on a gate-source voltage.

4. The voltage conversion circuit as set forth in claim 1, wherein when the first voltage is higher than the second voltage and the input signal goes to low level from high level, the signal transmission stages of the first level-shifting unit operate in a transition delay characteristic of ‘

FFS’ and

the signal transmission stages of the second level-shifting unit operate in a transition delay characteristic of ‘

FFS’

.

5. The voltage conversion circuit as set forth in claim 1, wherein when the first voltage is lower than the second voltage and the input signal goes to high level from low level, the signal transmission stages of the first level-shifting unit operate in a transition delay characteristic of ‘

SSS’ and

the signal transmission stages of the second level-shifting unit operate in a transition delay characteristic of ‘

SFF’

.

6. The voltage conversion circuit as set forth in claim 1, wherein when the first voltage is lower than the second voltage and the input signal goes to low level from high level, the signal transmission stages of the first level-shifting unit operate in a transition delay characteristic of ‘

SSF’ and

the signal transmission stages of the second level-shifting unit operate in a transition delay characteristic of ‘

SSF’

.

7. The voltage conversion circuit as set forth in claim 1, wherein the first level-shifting unit comprises:

a first inverter connected to the input terminal;

a second inverter connected to the output of the first inverter; and

a first differential amplifier driving the output terminal with one of the second voltage and a ground voltage in response to outputs of the first and second inverters,

wherein the first and second inverters are supplied with the first voltage, and the first differential amplifier is supplied with the second voltage.

8. The voltage conversion circuit as set forth in claim 7, wherein the first level-shifting unit further comprises an isolation circuit to electrically disconnect the output terminal from a first cross-coupling node of the first differential amplifier.

9. The voltage conversion circuit as set forth in claim 8, wherein the second level-shifting unit comprises:

a third inverter connected to the input terminal;

a second differential amplifier generating a signal with one of the second voltage and a ground voltage in response to the input signal and an output of the third inverter; and

a fourth inverter connected between an output of the second differential amplifier and the output terminal,

wherein the third inverter is supplied with the first voltage, and the second differential amplifier and the fourth inverter are supplied with the second voltage.

10. The voltage conversion circuit as set forth in claim 9, wherein the isolation circuit comprises:

a PMOS transistor connected between the second voltage and the output terminal, having a gate coupled to a second cross-coupling node of the first differential amplifier; and

a NMOS transistor connected between the output terminal and the ground voltage, having a gate coupled to the output of the second differential amplifier.

11. The voltage conversion circuit as set forth in claim 7, wherein the second level-shifting unit comprises:

a second differential amplifier generating a signal with one of the second voltage and a ground voltage in response to the input signal and an output of the first inverter; and

a third inverter connected between an output of the second differential amplifier and the output terminal,

wherein the second differential amplifier and the third inverter are supplied with the second voltage.

12. The voltage conversion circuit as set forth in claim 7, wherein the second level-shifting unit comprises:

a first PMOS transistor connected between the second voltage and an internal node, having a gate coupled to a first cross-coupling node of the first differential amplifier;

a first NMOS transistor connected between the internal node and the ground voltage, having a gate coupled to the input terminal;

a second PMOS transistor connected between the second voltage and the first cross-coupling node, having a gate coupled to the internal node; and

a second NMOS transistor connected between the output terminal and the ground voltage, having a gate coupled to a second cross-coupling node of the first differential amplifier.

13. The voltage conversion circuit as set forth in claim 12, wherein the first cross-coupling node of the first differential amplifier is connected to the output terminal.

14. The voltage conversion circuit as set forth in claim 1, which further comprises:

an inverter connected to the output terminal, being supplied with the second voltage.

20. The voltage conversion circuit as set forth in claim 1, wherein the first level-shifting unit comprises:

a first inverter connected to the input terminal;

a second inverter connected to the output of the first inverter;

a first differential amplifier having first and second cross-coupling nodes and operating in response to outputs of the first and second inverter; and

a first isolation circuit to electrically disconnect the output terminal from the first cross-coupling node and drive the output terminal with one of the second voltage and a ground voltage in response to outputs from the second cross-coupling node and the second inverter,

wherein the first and second inverters are supplied with the first voltage, and the first differential amplifier and isolation circuit are supplied with the second voltage.

21. The voltage conversion circuit as set forth in claim 20, wherein the second level-shifting unit comprises:

a third inverter connected to the input terminal;

a second differential amplifier having third and fourth cross-coupling nodes and generating a signal with one of the second voltage and the ground voltage in response to the input signal and an output of the third inverter;

a second isolation circuit generating a signal with one of the second voltage and the ground voltage in response to outputs from the fourth cross-coupling node and the third inverter; and

a fourth inverter connected between an output of the second isolation circuit and the output terminal,

wherein the third inverter is supplied with the first voltage, and the second differential amplifier, the second isolation circuit, and the fourth inverter are supplied with the second voltage.

22. The voltage conversion circuit as set forth in claim 21, wherein the first isolation circuit comprises:

a PMOS transistor connected between the second voltage and the output terminal, having a gate coupled to a second cross-coupling node of the first differential amplifier; and

a NMOS transistor connected between the output terminal and the ground voltage, having a gate coupled to the output of the second differential amplifier.

23. The voltage conversion circuit as set forth in claim 21, wherein the second isolation circuit comprises:

a PMOS transistor connected between the second voltage and an input of the fourth inverter, having a gate coupled to the fourth cross-coupling node of the second differential amplifier; and

a NMOS transistor connected between the input of the fourth inverter and the ground voltage, having a gate coupled to the output of the third inverter.

24. The voltage conversion circuit as set forth in claim 20, wherein the second level-shifting unit comprises:

a second differential amplifier having third and fourth cross-coupling nodes and generating a signal with one of the second voltage and the ground voltage in response to the output of the first inverter and the input signal;

a second isolation circuit generating a signal with one of the second voltage and the ground voltage in response to outputs from the fourth cross-coupling node and the first inverter; and

a fourth inverter connected between an output of the second isolation circuit and the output terminal,

wherein the second differential amplifier, the second isolation circuit, and the fourth inverter are supplied with the second voltage.

25. The voltage conversion circuit as set forth in claim 24, wherein the second isolation circuit comprises:

a PMOS transistor connected between the second voltage and an input of the fourth inverter, having a gate coupled to the fourth cross-coupling node of the second differential amplifier; and

a NMOS transistor connected between the input of the fourth inverter and the ground voltage, having a gate coupled to the output of the first inverter.

26. The voltage conversion circuit as set forth in claim 7, wherein the first level-shifting unit further comprises a third inverter connected between an output of the first differential amplifier and the output terminal.

27. The voltage conversion circuit as set forth in claim 8, wherein the second level-shifting unit comprises:

a second differential amplifier having third and fourth cross-coupling nodes and generating a signal with one of the second voltage and the ground voltage in response to the input signal and an output of the first inverter;

a second isolation circuit generating a signal with one of the second voltage and the ground voltage in response to outputs from the fourth cross-coupling node and the first inverter; and

a fourth inverter connected between an output of the second isolation circuit and the output terminal,

wherein the the second differential amplifier, the second isolation circuit, and the third inverter are supplied with the second voltage.

28. The voltage conversion circuit as set forth in claim 1, wherein the first level-shifting unit comprises:

a first inverter connected to the input terminal;

a second inverter connected to the output of the first inverter;

a first differential amplifier generating a signal with one of the second voltage and a ground voltage in response to the output of the first inverter and the output of the second inverter; and

a third inverter connected between an output of the first differential amplifier and the output terminal,

wherein the first inverter and second inverter are supplied with the first voltage, and the first differential amplifier and the third inverter are supplied with the second voltage.

29. The voltage conversion circuit as set forth in claim 28, wherein the second level-shifting unit comprises:

a fourth inverter connected to the input terminal;

a second differential amplifier generating a signal with one of the second voltage and a ground voltage in response to the input signal and an output of the fourth inverter; and

a fifth inverter and a sixth inverter, the fifth inverter being connected to an output of the second differential amplifier and the sixth inverter being connected to the output of the fifth inverter and the output terminal,

wherein the fourth inverter is supplied with the first voltage, and the second differential amplifier, the fifth inverter and the sixth inverter are supplied with the second voltage.

15. A voltage conversion circuit to generate an output signal of a second voltage from an input signal of a first voltage, comprising:

an input terminal receiving the input signal;

an output terminal generating the output signal; and

first and second level-shifting units connected between the input and output terminals in parallel,

wherein the first and second level-shifting units each have four signal transmission stages and different transition delay characteristics from each other so that rising and falling transition delays of the output signal are varied in the same rate when the first and second voltages are changed.

16. The voltage conversion circuit as set forth in claim 15, wherein when the first voltage is higher than the second voltage and the input signal goes to high level from low level, the signal transmission stages of the first level-shifting unit operate in a transition delay characteristic of ‘

FFFS’ and

the signal transmission stages of the second level-shifting unit operate in a transition delay characteristic of ‘

FSSS’

,

where the ‘

F’

represents a fast transition delay of a MOS transistor based on a gate-source voltage and the ‘

S’

represents a slow transition delay of a MOS transistor based on a gate-source voltage.

17. The voltage conversion circuit as set forth in claim 15, wherein when the first voltage is higher than the second voltage and the input signal goes to low level from high level, the signal transmission stages of the first level-shifting unit operate in a transition delay characteristic of ‘

FFSS’ and

the signal transmission stages of the second level-shifting unit operate in a transition delay characteristic of ‘

FFSS’

.

18. The voltage conversion circuit as set forth in claim 15, wherein when the first voltage is lower than the second voltage and the input signal goes to high level from low level, the signal transmission stages of the first level-shifting unit operate in a transition delay characteristic of ‘

SSSF’ and

the signal transmission stages of the second level-shifting unit operate in a transition delay characteristic of ‘

SFFF’

.

19. The voltage conversion circuit as set forth in claim 15, wherein when the first voltage is lower than the second voltage and the input signal goes to low level from high level, the signal transmission stages of the first level-shifting unit operate in a transition delay characteristic of ‘

SSFF’ and

the signal transmission stages of the second level-shifting unit operate in a transition delay characteristic of ‘

SSFF’

.