Phase locked loop with temperature compensation

• US 20060262623A1
• Filed: 07/14/2006
• Published: 11/23/2006
• Est. Priority Date: 10/15/2002
• Status: Abandoned Application

• Current Assignee: Sehat Sutardja
• Original Assignee: Sehat Sutardja
• Inventors: Sutardja, Sehat
• Application Number:
  US11/486,944
• Publication Number:
  US 20060262623A1
• Time in Patent Office: Days
• US Class Current: 365/211
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/315 the encapsulation having a cavity
• CPC Class Codes: H01L 23/345 Arrangements for heating thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/30107 Inductance
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H03B 5/04 Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
• CPC Class Codes: H03B 5/36 active element in amplifier being semiconductor device H03B5/323, H03B5/326 , H03B5/38 take precedence
• CPC Class Codes: H03L 1/026 by using a memory for digitally storing correction values H03L1/025 takes precedence
• CPC Class Codes: H03L 1/027 by using frequency conversion means which is variable with temperature, e.g. mixer, frequency divider, pulse add/substract logic circuit H03L1/023, H03L1/026 take precedence
• CPC Class Codes: H03L 1/04 Constructional details for maintaining temperature constant
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/099 : concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/1976 : using a phase accumulator for controlling the counter or frequency divider

Abstract

An integrated circuit comprises a temperature sensor that senses a temperature of the integrated circuit. A memory module stores oscillator data relating to calibrations and selects one of the oscillator calibrations as a function of the sensed temperature. An oscillator module generates a reference signal having a frequency. A phase locked loop module comprises a feedback loop having a feedback loop parameter. The phase locked loop module selectively adjusts the feedback loop parameter based on the selected one of the oscillator calibrations.

Claims

1. An integrated circuit comprising:

a temperature sensor that senses a temperature of said integrated circuit;

a memory module that stores oscillator data relating to calibrations and that selects one of said oscillator calibrations as a function of said sensed temperature;

an oscillator module that generates a reference signal having a frequency; and

a phase locked loop module comprising a feedback loop having a feedback loop parameter, wherein said phase locked loop module selectively adjusts said feedback loop parameter based on said selected one of said oscillator calibrations.

2. The integrated circuit of claim 1 wherein said phase locked loop module comprises a fractional phase locked loop module and said feedback loop parameter is a ratio of a scaling factor.

3. The integrated circuit of claim 2 wherein said fractional phase locked loop module comprises:

a phase frequency detector module that communicates with said oscillator module and that receives said reference frequency;

a charge pump module that communicates with said phase frequency detector module;

a voltage controlled oscillator module that communicates with said charge pump module and that generates an output frequency;

a scaling module that communicates with said voltage controlled oscillator and said phase frequency detector module and that selectively adjusts said output frequency first and second scaling factors,

wherein said scaling module adjusts a ratio of said first and second scaling factors based on said selected one of said oscillator calibrations.

4. The integrated circuit of claim 3, wherein said first and second scaling factors are divisors equal to N and N+1, and wherein N is an integer greater than zero.

5. The integrated circuit of claim 1 wherein said phase locked loop module comprises a Delta Sigma fractional phase locked loop module and said feedback loop parameter includes modulation of a scaling divisor.

6. The integrated circuit of claim 5 wherein said Delta Sigma fractional phase locked loop module comprises:

a phase frequency detector module that communicates with said oscillator module and that receives said reference frequency;

a charge pump module that communicates with said phase frequency detector module;

a voltage controlled oscillator module that communicates with said charge pump module and that generates an output frequency;

a scaling module that communicates with said voltage controlled oscillator and said phase frequency detector module and that selectively divides said output frequency by first and second scaling factors; and

a Sigma Delta modulator that adjusts modulation of said scaling module between said first and second scaling factors based on said selected one of said oscillator calibrations.

7. The integrated circuit of claim 6, wherein said first and second scaling factors are divisors equal to N and N+1, where N is an integer greater than zero.

8. An integrated circuit comprising:

temperature sensing means that senses a temperature of said integrated circuit;

memory means for storing oscillator data relating to calibrations and for selecting one of said oscillator calibrations as a function of said sensed temperature;

oscillator means for generating a reference signal having a frequency; and

phase locked loop means, comprising a feedback loop having a feedback loop parameter, for selectively adjusting said feedback loop parameter based on said selected one of said oscillator calibrations.

9. The integrated circuit of claim 8 wherein said phase locked loop means comprises fractional phase locked loop means for providing feedback and said feedback loop parameter is a ratio of a scaling factor.

10. The integrated circuit of claim 9 wherein said fractional phase locked loop means comprises:

phase frequency detector means, that communicates with said oscillator means, for receiving said reference frequency;

charge pump means, that communicates with said phase frequency detector means, for pumping;

voltage controlled oscillator means, that communicates with said charge pump means, for generating an output frequency;

scaling means, that communicates with said voltage controlled oscillator and said phase frequency detector means, for selectively adjusting said output frequency first and second scaling factors,

wherein said scaling means adjusts a ratio of said first and second scaling factors based on said selected one of said oscillator calibrations.

11. The integrated circuit of claim 10, wherein said first and second scaling factors are divisors equal to N and N+1, and wherein N is an integer greater than zero.

12. The integrated circuit of claim 8 wherein said phase locked loop means comprises Delta Sigma fractional phase locked loop means for providing feedback and said feedback loop parameter includes modulation of a scaling divisor.

13. The integrated circuit of claim 12 wherein said Delta Sigma fractional phase locked loop comprises:

phase frequency detector means, that communicates with said oscillator means, for receiving said reference frequency;

charge pump means, that communicates with said phase frequency detector means, for pumping;

voltage controlled oscillator means, that communicates with said charge pump means, for generating an output frequency;

scaling means, that communicates with said voltage controlled oscillator and said phase frequency detector means, for selectively dividing said output frequency by first and second scaling factors; and

Sigma Delta modulating means for adjusting modulation of said scaling means between said first and second scaling factors based on said selected one of said oscillator calibrations.

14. The integrated circuit of claim 13, wherein said first and second scaling factors are divisors equal to N and N+1, where N is an integer greater than zero.

15. A method for operating an integrated circuit comprising:

sensing a temperature of said integrated circuit;

storing oscillator data relating to calibrations;

selecting one of said oscillator calibrations as a function of said sensed temperature;

generating a reference signal having a frequency; and

selectively adjusting a feedback loop parameter of a phase locked loop based on said selected one of said oscillator calibrations.

16. The method of claim 15 wherein said feedback loop parameter is a ratio of a scaling factor.

17. The method of claim 16 further comprising:

selectively adjusting an output frequency by first and second scaling factors; and

adjusting a ratio of said first and second scaling factors based on said selected one of said oscillator calibrations.

18. The method of claim 17 wherein said first and second scaling factors are divisors equal to N and N+1, and wherein N is an integer greater than zero.

19. The method of claim 15 wherein said feedback loop parameter includes modulation of a scaling divisor.

20. The method of claim 19 further comprising:

selectively dividing said output frequency by first and second scaling factors; and

adjusting modulation between said first and second scaling factors based on said selected one of said oscillator calibrations.

21. The method of claim 20 wherein said first and second scaling factors are divisors equal to N and N+1, where N is an integer greater than zero.