Semiconductor memory device and fabrication thereof

• US 20060263970A1
• Filed: 11/29/2005
• Published: 11/23/2006
• Est. Priority Date: 05/20/2005
• Status: Active Grant

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: Winbond Electronics Corporation
• Inventors: Jang, Wen-Yueh
• Granted Patent: US 7,332,390 B2
• Time in Patent Office: Days
• US Class Current: 438/238
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H10B 12/0385 Making a connection between the transistor and the capacitor, e.g. buried strap

Abstract

A semiconductor memory device and fabrication method thereof. In a semiconductor memory device, each memory cell comprises a deep trench and a capacitor disposed on the lower portion thereof. A collar oxide layer having a first second sidewalls is disposed on the deep trench. The top of the first sidewall is at the same height as the surface of the semiconductor substrate. The top of the second sidewall is substantially equal to the top of the capacitor. The memory cell further comprises a buried conductor layer disposed on the second sidewall and the capacitor and a buried strap adjoining the buried conductive layer, and a transistor disposed on the surface of the semiconductor substrate and electrically connected to the capacitor through the buried strap and the buried conductive layer.

Claims

1. A method for forming a semiconductor memory device, comprising:

providing a semiconductor substrate, comprising a plurality of deep trenches, each comprising a first side, a second side opposite the first side and a third side between the first side and the second side, wherein the semiconductor substrates are defined to form a plurality of active areas, overlapping with a portion of the deep trench;

forming a collar oxide layer in each deep trench, comprising a first side portion, a second side portion and a third side portion, adjacent to the first, second and third side of the deep trench respectively;

forming a capacitor at a lower portion of each trench, comprising a bottom electrode, a top electrode and a dielectric layer between the bottom electrode and the top electrode, wherein top of the top electrode is between the top and bottom of the collar oxide layer;

removing a portion of the second side portion of the collar oxide layer, wherein subsequent to the removing step, the top of the second side portion is at substantially the same level as top of the top electrode;

forming a buried conductive layer overlying the top electrode and the second side portion;

forming a buried strap in a portion of the semiconductor substrate adjacent to the second side of the deep trench, wherein the buried strap is adjacent to the buried conductive layer; and

forming a transistor on a portion of the semiconductor substrate adjacent to the second side of the deep trench, wherein the transistor comprises a source, a drain and a gate, and the drain is electrically connected to the top electrode of the capacitor through the buried strap and the buried conductive layer.

2. The method for forming a semiconductor memory device as claimed in claim 1, further comprising, prior to the step of forming the transistors:

forming a patterned photoresist layer, covering the deep trenches and the active areas;

removing a portion of the semiconductor substrate and the third side portion by photolithography and etching to form an opening at the third side portion adjacent to the deep trench, wherein the opening is parallel to the active areas; and

forming an isolation layer in the opening.

3. The method for forming a semiconductor memory device as claimed in claim 1, further comprising:

forming a dielectric layer on the semiconductor substrate;

forming a plurality of plugs in the dielectric layer, electrically connected to a transistor; and

forming a plurality of parallel bit lines on the dielectric layer, electrically connecting to the plugs, wherein the bit lines are electrically connected to the transistors through the plugs.

4. The method for forming a semiconductor memory device as claimed in claim 1, wherein the step of forming the transistor comprises:

forming a plurality of word lines on the semiconductor substrate, passing through the active areas;

implanting each active area of the semiconductor substrate to form two doped regions adjacent to opposite sides of the word lines.

5. The method for forming a semiconductor memory device as claimed in claim 4, wherein the word lines are gates of the transistors.

6. The method for forming a semiconductor memory device as claimed in claim 4, wherein the two doped regions are the source and drain of one of the transistors respectively.

7. The method for forming a semiconductor memory device as claimed in claim 1, wherein the doped conductive layer is a doped polysilicon.

8. The method for forming a semiconductor memory device as claimed in claim 1, wherein the transistor is a MOSFET transistor.

9. The method for forming a semiconductor memory device as claimed in claim 1, wherein the buried strap comprises dopants, and the method for forming a semiconductor memory device further comprises a thermal process, annealing the buried conductive layer to out diffuse the dopants therein, forming a buried strap in a portion of the semiconductor substrate adjacent to one side of the buried conductive layer.

10. A semiconductor memory device, comprising:

a semiconductor substrate;

a plurality of memory units overlying the semiconductor substrate, each comprising;

a deep trench overlying the semiconductor substrate, comprising a first side and a second side opposite the first side;

a capacitor disposed in a lower portion of the deep trench, comprising a bottom electrode, a top electrode and a dielectric layer threrebeteen;

a collar oxide layer disposed on sidewall of the deep trench, comprising a first side portion at the first side of the deep trench and a second side portion at the second side of the deep trench, wherein top of the first side portion is substantially as the same level as the semiconductor substrate surface, and top of the second side portion is substantially as the same level as the top electrode;

a buried conductive layer, disposed overlying the top electrode and the second side portion of the collar oxide layer;

a MOS transistor, disposed overlying an active area of the semiconductor substrate, wherein the active area is adjacent to the second side of the deep trench, the MOS transistor comprises a gate, a source and a drain, and the drain is electrically connected to the capacitor through the buried conductive layer; and

an isolation layer, interposed between two adjacent memory units and parallel with the active areas.

11. The semiconductor memory device as claimed in claim 10, wherein the collar oxide layer further comprises a third side portion interposed between the first side portion and the second side portion, wherein top of the third side portion is lower than top of the first side portion.

12. The semiconductor memory device as claimed in claim 11, wherein the isolation layer is adjacent to the third portion, and surrounds the buried conductive layer.

13. The semiconductor memory device as claimed in claim 10, wherein the second side portions of the collar oxide layers are disposed at the same positions of the deep trenches.

14. The semiconductor memory device as claimed in claim 10, wherein each memory unit further comprises a buried strap adjacent to one side of the buried conductive layers.