Method of forming integrated circuitry

• US 20060264019A1
• Filed: 07/31/2006
• Published: 11/23/2006
• Est. Priority Date: 12/03/2004
• Status: Active Grant

• Current Assignee: John K. Zahurak, Kunal R. Parekh
• Original Assignee: John K. Zahurak, Kunal R. Parekh
• Inventors: Parekh, Kunal R., Zahurak, John K.
• Granted Patent: US 7,439,138 B2
• Time in Patent Office: Days
• US Class Current: 438/595
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/43 comprising only one type of peripheral transistor

Abstract

The invention includes methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors. In one implementation, conductive metal silicide is formed on some areas of a substrate and not on others. In one implementation, conductive metal silicide is formed on a transistor source/drain region and which is spaced from an anisotropically etched sidewall spacer proximate a gate of the transistor.

Claims

1-51. -51. (canceled)

52. A method of forming integrated circuitry comprising:

providing a substrate comprising a first circuitry area and a second circuitry area, the first circuitry area comprising a first pair of spaced adjacent conductive structures received over the substrate in at least a first cross-section, the second circuitry area comprising a second pair of spaced adjacent conductive structures received over the silicon-comprising substrate in at least a second cross-section, the conductive structures of the second pair being spaced further from one another in the second cross-section than are those of the first pair in the first cross-section, first anisotropically etched insulative sidewall spacers being received over sidewalls of the conductive structures of the first and second pair;

depositing a masking material between the conductive structures of each of the first and second pairs; and

anisotropically etching the masking material effective to form sidewall spacers over the first anisotropically etched sidewall spacers of each of the conductive structures of the second pair and leave at least some of the masking material spanning between the first anisotropically etched sidewall spacers of each of the conductive structures of the first pair at the conclusion of said anisotropically etching.

53. The method of claim 52 wherein the masking material is electrically insulative.

54. The method of claim 53 wherein the masking material comprises silicon nitride.

55. The method of claim 53 wherein the masking material comprises silicon dioxide.

56. The method of claim 52 wherein the masking material comprises amorphous carbon.

57. The method of claim 52 wherein the masking material comprises transparent carbon.

58. The method of claim 52 wherein the masking material is electrically conductive.

59. The method of claim 58 wherein the masking material comprises a metal nitride.

60. The method of claim 59 wherein the masking material comprises tungsten nitride.

61. The method of claim 59 wherein the masking material comprises titanium nitride.

62. The method of claim 52 wherein the masking material is semiconductive.

65. The method of claim 52 comprising after the conclusion of said anisotropically etching, removing at least some of said masking material from between the conductive structures of the first pair.

66. The method of claim 52 comprising after the conclusion of said anisotropically etching, removing all of said masking material from between the conductive structures of the first pair.

67. The method of claim 52 comprising after the conclusion of said depositing anisotropically etching, removing all of said masking material from the substrate.

69. The method of claim 52 wherein the depositing of the masking material through said anisotropically etching of the masking material occurs without any photolithographic patterning anywhere on the substrate.

63-64. -64. (canceled)

68. (canceled)

70-82. -82. (canceled)