System for identification of defects on circuits or other arrayed products

• US 20060265185A1
• Filed: 07/25/2006
• Published: 11/23/2006
• Est. Priority Date: 06/10/2003
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Yashchin, Emmanuel, Trapp, Brian, Lanzerotti, Mary, Takken, Asya, Landers, Christina
• Application Number:
  US11/493,092
• Publication Number:
  US 20060265185A1
• Time in Patent Office: Days
• US Class Current: 702/181
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

A system and method is disclosed for assessing a probability of failure of operation of a semiconductor wafer. The method includes inputting risk factor data into a memory and inputting a plurality of wafers into a semiconductor fabrication manufacturing process. A subset of wafers is selected to obtain a sample population and at least one region of each wafer of the sample population is inspected. Circuit design data associated with each wafer of the sample population is obtained and one or more defects that present an increased risk to the operation of a particular wafer are identified. The identification is a function of the risk factor data, the inspecting step and the circuit design data. A probability of semiconductor wafer failure is calculated.

Claims

1-34. -34. (canceled)

35. A method for generating a probability model for assessing the probability of failure of a semiconductor chip due to at least one defect, the method comprising:

obtaining defect characteristic data;

obtaining chip characteristic data;

specifying a probability relationship between the defect characteristic data and the chip characteristic data, wherein said probability relationship includes at least one first parameter value;

estimating at least one second parameter value for said probability relationship based on defect characteristic data and chip characteristic data; and

generating a probability model comprising said probability relationship and said at least one second parameter value.

36. The method of claim 35, wherein the probability relationship comprises a risk map for the semiconductor chip.

37. The method of claim 36, further comprising:

generating a tool inspection area for the semiconductor chip as a function of the risk map; and

inspecting the tool inspection area for further defects on the semiconductor chip.

38. The method of claim 35, wherein the probability relationship comprises defect location risk, defect location, and defect size.

39. The method of claim 35, wherein the defect characteristic data comprises a list of defects, the first parameter value comprises defect location risk, the second parameter value comprises probability of failure of the semiconductor chip by each defect of the list, and the probability model comprises an accumulated risk factor comprising an accumulated probability of failure of the semiconductor chip for all defects of the list.

40. The method of claim 35, wherein the second parameter value comprises probability of failure of the semiconductor chip by each particular defect.

41. The method of claim 35, further comprising:

testing the semiconductor chip for compliance with the probability model; and

updating the chip characteristic data based on the testing.

42. The method of claim 35, wherein the chip characteristic data comprises circuit design data.

43. The method of claim 35, wherein the defect characteristic data comprises at least one of:

an impurity, an occlusion, and a deformity.

44. The method of claim 35, wherein the defect characteristic data is obtained from an inspection of the semiconductor chip.

45. The method of claim 44 wherein the inspection of the semiconductor chip is for each mask level of the semiconductor chip.

46. The method of claim 35, further comprising:

evaluating a semiconductor chip for failure using the probability model during an interim fabrication step of said chip.

47. The method of claim 46, wherein the evaluating is in real time with the interim fabrication step.

48. The method of claim 35, further comprising:

using the probability model to determine a number of wafer starts needed to meet a particular customer commitment.

49. The method of claim 35, wherein the defect characterization data comprises a list of defects, the method further comprising:

ranking at least some defects of the list with a likelihood of being responsible for failure of a semiconductor chip.

50. A computer program, tangibly embodied on a medium readable by a computer, to perform actions directed toward assessing the probability of failure of a semiconductor chip due to at least one defect, the actions comprising:

from inputs of defect characteristic data and chip characteristic data, specifying a probability relationship between the defect characteristic data and the chip characteristic data, wherein said probability relationship includes at least one first parameter value;

estimating at least one second parameter value for said probability relationship based on defect characteristic data and chip characteristic data; and

generating a probability model comprising said probability relationship and said at least one second parameter value.

51. The computer program of claim 50, wherein the probability relationship comprises a risk map for the semiconductor chip.

52. The computer program of claim 51, the actions further comprising:

generating a tool inspection area for the semiconductor chip as a function of the risk map.

53. The computer program of claim 50, wherein the probability relationship comprises defect location risk, defect location, and defect size.

54. The computer program of claim 50, wherein the defect characteristic data comprises a list of defects, the first parameter value comprises defect location risk, the second parameter value comprises probability of failure of the semiconductor chip by each defect of the list, and the probability model comprises an accumulated risk factor comprising an accumulated probability of failure of the semiconductor chip for all defects of the list.

55. The computer program of claim 50, wherein the second parameter value comprises probability of failure of the semiconductor chip by one particular defect.

56. The computer program of claim 50, the actions further comprising:

updating the chip characteristic data based on a feedback of actual testing of the semiconductor chip as compared to the probability model.

57. The computer program of claim 50, wherein the chip characteristic data comprises circuit design data.

58. The computer program of claim 50, wherein the defect characteristic data comprises at least one of:

an impurity, an occlusion, and a deformity.

59. The computer program of claim 50, wherein the defect characteristic data is for each mask level of the semiconductor chip.

60. The computer program of claim 50, the actions further comprising:

evaluating a semiconductor chip for failure using the probability model during an interim fabrication step of said chip.

61. The computer program of claim 60, wherein the evaluating is in real time with the interim fabrication step.

62. The computer program of claim 50, the actions further comprising:

using the probability model to determine a number of wafer starts needed to meet a particular customer commitment.

63. The computer program of claim 50, wherein the defect characterization data comprises a list of defects, the actions further comprising:

ranking at least some defects of the list with a likelihood of being responsible for failure of a semiconductor chip.