Layout design program, layout design device and layout design method for semiconductor integrated circuit

• US 20060265678A1
• Filed: 05/18/2006
• Published: 11/23/2006
• Est. Priority Date: 05/19/2005
• Status: Active Grant

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Okabe, Hideyuki
• Granted Patent: US 7,516,434 B2
• Time in Patent Office: Days
• US Class Current: 716/113
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

A computer program product for floorplanning design of a semiconductor integrated circuit, embodied on a computer-readable medium and including code that, when executed, causes a computer to perform the following steps (a) to (d). The step (a) is the step of placing circuit blocks based on a netlist. The step (b) is the step of estimating an interconnection length between two of the placed circuit blocks based on the netlist and positions of the placed circuit blocks. The step (c) is the step of judging whether the estimated interconnection length satisfies timing constraints for connections among the circuit blocks, based on relation data indicating relations among interconnection lengths and timings. The step (d) is the step of outputting the judgment result.

Claims

1. A computer program product for floorplanning design of a semiconductor integrated circuit, embodied on a computer-readable medium and comprising code that, when executed, causes a computer to perform the following:

(a) placing a plurality of circuit blocks based on a netlist;

(b) estimating an interconnection length between two of said placed plurality of circuit blocks based on said netlist and positions of said placed plurality of circuit blocks;

(c) judging whether or not said estimated interconnection length satisfies timing constraints for connections among said plurality of circuit blocks, based on relation data indicating relations among interconnection lengths and timings; and

(d) outputting said judgment result.

2. The computer program product according to claim 1, wherein said steps (b) to (d) are executed every time when one circuit block is additionally placed.

3. The computer program product according to claim 1, wherein said relation data indicates relations among allowable interconnection lengths and operational frequencies, and

said step (c) includes:

(c1) judging whether or not said estimated interconnection length satisfies an allowable interconnection length based on relation data,

said allowable interconnection length corresponds to an operational frequency which is specified by said timing constraints.

4. The computer program product according to claim 1, wherein said relation data includes a delay time per unit interconnection length,

said step (c) includes:

(c2) calculating a delay time based on said estimated interconnection length and said delay time per unit interconnection length, and

(c3) judging whether or not said calculated delay time satisfies said timing constraints.

5. The computer program product according to claim 1, wherein said step (d) includes:

(d1) displaying said judgment result superimposed onto said placed plurality of circuit blocks in a display device.

6. The computer program product according to claim 1, wherein said step (a) includes:

(a1) determining a placement position of a first circuit block of said plurality of circuit blocks based on numbers of connected interconnections among said plurality of circuit blocks, said first circuit block is not placed yet.

7. The computer program product according to claim 6, wherein said step (b) includes:

(b1) estimating said interconnection length based on a first coordinate of a first terminal and a second coordinate of a second terminal,

said first terminal represents terminals of said first circuit block, to be connected to a second circuit block,

said second circuit block is one of said plurality of circuit blocks, has the connection relation to said first circuit block and is already placed, and

said second terminal represents terminals of said second circuit block, to be connected to said first circuit block.

8. The computer program product according to claim 7, wherein candidates of said first terminal are a first center point indicating a geometric center of said first circuit block, a first closest point indicating the closest point of said first circuit block to said second circuit block, and a first farthest point indicating the farthest point of said first circuit block to said second circuit block,

candidates of said second terminal are a second center point indicating a geometric center of said second circuit block, a second closest point indicating the closest point of said second circuit block to said first circuit block, and a second farthest point indicating the farthest point of said second circuit block to said first circuit block, and

said step (b1) includes:

(b11) selecting one of a first interconnection length, a second interconnection length and a third interconnection length as said interconnection length, wherein said first interconnection length is a length of an interconnection connecting said first center point and said second center point, said second interconnection length is a length of an interconnection connecting said first closest point and said second closest point, and said third interconnection length is a length of an interconnection connecting said first farthest point and said second farthest point.

9. The computer program product according to claim 7, wherein at least one of said first circuit block and said second circuit block includes a placed cell,

said step (b) includes:

(b2) estimating said interconnection length based on a terminal of said placed cell as corresponding at least one of said first terminal and said second terminal.

10. The computer program product according to claim 7, wherein at least one of said first circuit block and said second circuit block is a layer block, of which a position of a terminal to be connected to anther circuit block is set,

said step (b) includes:

(b3) estimating said interconnection length based on said terminal to be connected to said another circuit block as corresponding at least one of said first terminal and said second terminal.

11. The computer program product according to claim 1, wherein said timing constraints includes operational frequencies, each of which is set correspondingly to each interconnection.

12. A layout design device for floorplanning design of a semiconductor integrated circuit, comprising:

a storing section configured to store a netlist, timing constraints for connections among a plurality of circuit blocks, and relation data indicating relations among interconnection lengths and timings;

a circuit block placing section configured to place said plurality of circuit blocks based on said netlist;

an interconnection length estimating section configured to estimate an interconnection length between two of said placed plurality of circuit blocks based on said netlist and positions of said placed plurality of circuit blocks;

a judging section configured to judge whether or not said estimated interconnection length satisfies said timing constraints based on said relation data; and

a displaying section configured to output said judgment result.

13. The layout design device according to claim 12, wherein every time when one circuit block is additionally placed by said circuit block placing section, said interconnection length estimating section estimates said interconnection length, said judging section judges whether or not said estimated interconnection length satisfies said timing constraints and said displaying section outputs said judgment result.

14. The layout design device according to claim 12, wherein said relation data indicates relations among allowable interconnection lengths and operational frequencies, and

said judging section judges whether or not said estimated interconnection length satisfies an allowable interconnection length based on relation data,

said allowable interconnection length corresponds to an operational frequency which is specified by said timing constraints.

15. The layout design device according to claim 12, wherein said relation data includes a delay time per unit interconnection length,

said judging section calculates a delay time based on said estimated interconnection length and said delay time per unit interconnection length, and judges whether or not said calculated delay time satisfies said timing constraints.

16. The layout design device according to claim 12, wherein said displaying section displays said judgment result superimposed onto said placed plurality of circuit blocks in a display device.

17. The layout design device according to claim 12, wherein said circuit block placing section determines a placement position of a first circuit block of said plurality of circuit blocks based on numbers of connected interconnections among said plurality of circuit blocks, said first circuit block is not placed yet.

18. The layout design device according to claim 17, wherein said interconnection length estimating section estimates said interconnection length based on a first coordinate of a first terminal and a second coordinate of a second terminal,

said first terminal represents terminals of said first circuit block, to be connected to a second circuit block,

said second circuit block is one of said plurality of circuit blocks, has the connection relation to said first circuit block and is already placed, and

said second terminal represents terminals of said second circuit block, to be connected to said first circuit block.

19. The layout design device according to claim 18, wherein candidates of said first terminal are a first center point indicating a geometric center of said first circuit block, a first closest point indicating the closest point of said first circuit block to said second circuit block, and a first farthest point indicating the farthest point of said first circuit block to said second circuit block,

candidates of said second terminal are a second center point indicating a geometric center of said second circuit block, a second closest point indicating the closest point of said second circuit block to said first circuit block, and a second farthest point indicating the farthest point of said second circuit block to said first circuit block, and

said interconnection length estimating section selects one of a first interconnection length, a second interconnection length and a third interconnection length as said interconnection length, wherein said first interconnection length is a length of an interconnection connecting said first center point and said second center point, said second interconnection length is a length of an interconnection connecting said first closest point and said second closest point, and said third interconnection length is a length of an interconnection connecting said first farthest point and said second farthest point.

20. The layout design device according to claim 18, wherein at least one of said first circuit block and said second circuit block includes a placed cell,

said interconnection length estimating section estimates said interconnection length based on a terminal of said placed cell as corresponding at least one of said first terminal and said second terminal.

21. The layout design device according to claim 18, wherein at least one of said first circuit block and said second circuit block is a layer block, of which a position of a terminal to be connected to anther circuit block is set,

said interconnection length estimating section estimates said interconnection length based on said terminal to be connected to said another circuit block as corresponding at least one of said first terminal and said second terminal.

22. The layout design device according to claim 12, wherein said timing constraints includes operational frequencies, each of which is set correspondingly to each interconnection.

23. A layout design method for a semiconductor integrated circuit for floorplanning design, comprising:

(a) placing a plurality of circuit blocks based on a netlist;

(b) estimating an interconnection length between two of said placed plurality of circuit blocks based on said netlist and positions of said placed plurality of circuit blocks;

(c) judging whether or not said estimated interconnection length satisfies timing constraints for connections among said plurality of circuit blocks, based on relation data indicating relations among interconnection lengths and timings; and

(d) outputting said judgment result.

24. The layout design method according to claim 23, wherein said steps (b) to (d) are executed every time when one circuit block is additionally placed.

25. The computer program product according to claim 23, wherein said relation data indicates relations among allowable interconnection lengths and operational frequencies, and

said step (c) includes:

(c1) judging whether or not said estimated interconnection length satisfies an allowable interconnection length based on relation data,

said allowable interconnection length corresponds to an operational frequency which is specified by said timing constraints.

26. The layout design method according to claim 23, wherein said relation data includes a delay time per unit interconnection length,

said step (c) includes:

(c2) calculating a delay time based on said estimated interconnection length and said delay time per unit interconnection length, and

(c3) judging whether or not said calculated delay time satisfies said timing constraints.

27. The layout design method according to claim 23, wherein said step (d) includes:

(d1) displaying said judgment result superimposed onto said placed plurality of circuit blocks in a display device.