Manufacturing Aware Deisgn and Design Aware Manufacturing

• US 20060265679A1
• Filed: 05/20/2006
• Published: 11/23/2006
• Est. Priority Date: 05/20/2005
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Scheffer, Louis K., Fujimura, Akira
• Granted Patent: US 7,712,064 B2
• Time in Patent Office: Days
• US Class Current: 716/52
• CPC Class Codes: G03F 7/70091 Illumination settings, i.e. intensity distribution in the pupil plane or angular distribution in the field plane; On-axis or off-axis settings, e.g. annular, dipole or quadrupole settings; Partial coherence control, i.e. sigma or numerical aperture [NA]
• CPC Class Codes: G03F 7/70125 Use of illumination settings tailored to particular mask patterns details of setting means G03F7/70091
• CPC Class Codes: G03F 7/70425 Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
• CPC Class Codes: G05B 2219/35028 Adapt design as function of manufacturing merits, features, for manufacturing, DFM
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

Some embodiments of the invention provide a manufacturing aware process for designing an integrated circuit (“IC”) layout. The process receives a manufacturing configuration that specifies a set of manufacturing settings for a set of machines to be used to manufacture an IC based on the IC layout. The process defines a set of design rules based on the specified manufacturing configuration. The process uses the set of design rules to design the IC layout. Some embodiments of the invention provide a design aware process for manufacturing an integrated circuit (“IC”). The process receives an IC design with an associated set of design properties. The process specifies a manufacturing configuration that specifies a set of manufacturing settings for a set of machines to be used to manufacture the IC, where the specified set of manufacturing settings are based on the set of design properties. The process manufactures the IC based on the manufacturing settings.

Claims

1. A manufacturing aware process for designing an integrated circuit (“

IC”

) layout, the process comprising;

a. receiving a manufacturing configuration that specifies a set of manufacturing settings for a set of machines to be used to manufacture an IC based the IC layout;

b. defining a set of design rules based on the specified manufacturing configuration; and

c. using the set of design rules to design the IC layout.

2. The process of claim 1, wherein the set of manufacturing settings comprises a specified dipole lens for a first layer of the IC layout.

3. The process of claim 2, wherein defining the set of design rules comprises defining a narrow route in a first direction of the first layer and a wide route in a second direction of the first layer.

4. The process of claim 3, wherein the dipole lens comprises two poles that are vertically aligned, wherein the first direction is a horizontal direction.

5. The process of claim 3, wherein the dipole lens comprises two poles that are horizontally aligned, wherein the first direction is a vertical direction.

6. The process of claim 3, wherein the dipole lens comprises two poles that are 45°

diagonally aligned, wherein the first direction is a 135°

diagonal direction.

7. The process of claim 1, wherein the set of manufacturing settings comprises a specified first dipole lens and a second dipole lens for a first layer for the IC layout.

8. The process of claim 1, wherein the set of manufacturing settings comprises an aperture setting for an illuminator.

9. The process of claim 1, wherein set of manufacturing settings comprises a specified nominal exposure.

10. The process of claim 1, wherein the set of manufacturing settings comprises a specified light wavelength for an illuminator.

11. The process of claim 10, wherein the set of design rules based on a specified shorter light wavelength specify smaller dimensional attributes for elements of the IC layout than the set of design rules based on a specified longer light wavelength.

12. The process of claim 11, wherein the element is a contact.

13. The process of claim 11, wherein the element is a route.

14. The process of claim 11, wherein the element is a module.

15. The process of claim 10, wherein the set of design rules based on a specified shorter light wavelength specify a denser IC layout than the set of design rules based on a specified longer light wavelength.

16. A design aware process for manufacturing an integrated circuit (“

IC”

), the process comprising;

a. receiving an IC design with an associated set of design properties;

b. specifying a manufacturing configuration that specifies a set of manufacturing settings for a set of machines to be used to manufacture the IC, wherein the specified set of manufacturing settings are based on the set of design properties; and

c. manufacturing the IC based on the manufacturing settings.

17. The process of claim 16, wherein the set of design properties include a set of design rules for specifying a particular dimensional attribute for a set of elements for a particular layer of the IC layout.

18. The process of claim 17, wherein the set of manufacturing settings specify a particular aperture.

19. The process of claim 18, wherein the set of manufacturing settings specify a nominal exposure.

20. The process of claim 18, wherein the set of manufacturing settings specify a particular stepper lens.

21. The process of claim 17, wherein the set of design properties includes a set of characteristics of the design.

22. The process of claim 21, wherein the set of design characteristics includes a particular dimensional attribute for a set of elements for a particular layer of the IC layout.

23. The process of claim 21, wherein the set of design characteristics includes a particular amount of wiring in a particular direction on a particular layer.