DMOS transistor with a poly-filled deep trench for improved performance

• US 20060267044A1
• Filed: 09/23/2005
• Published: 11/30/2006
• Est. Priority Date: 05/24/2005
• Status: Active Grant

• Current Assignee: Robert Kuo-Chang Yang
• Original Assignee: Robert Kuo-Chang Yang
• Inventors: Yang, Robert Kuo-Chang
• Granted Patent: US 7,535,057 B2
• Time in Patent Office: Days
• US Class Current: 257/141
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7823 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

Floating trenches are arranged in the layout of a single DMOS transistor or an array of DMOS transistors, the array forming a single power transistor. The trenches run perpendicular to the gate width direction either outside the transistor(s) or between rows of the transistors. The floating trenches are at a potential between the drain voltage and the substrate voltage (usually ground). The potentials of the opposing trenches cause merging depletion regions under the gate in the drift region. This merging shapes the field lines so as to increase the breakdown voltage of the transistor and provide other advantages. The technique is applicable to both lateral and vertical DMOS transistors.

Claims

1. A transistor structure comprising:

a DMOS transistor comprising a source, a drain, a body region, a gate, and a drift region between the drain and the body region, the gate having a width dimension; and

parallel opposing floating trenches, containing a conductive or semiconductor material, with the gate width dimension substantially perpendicular to the opposing floating trenches,

wherein the opposing floating trenches are arranged such that an operating bias voltage applied to the drain capacitively couples a potential to the opposing floating trenches, the potential being lower than the drain voltage, and creates a space charge region (SCR) in the drift region by each opposing floating trench that merges under the gate.

2. The structure of claim 1 wherein the DMOS transistor comprises a two-dimensional array of DMOS transistors arranged in rows, each DMOS transistor comprising a source, a drain, a body region, a gate, and a drift region between the drain and the body region, the gate having a width dimension substantially perpendicular to a row of DMOS transistors, wherein the parallel opposing floating trenches run along a plurality of rows of DMOS transistors, there being at least a portion of a row of DMOS transistors between a pair of opposing floating trenches, with the gate width dimension substantially perpendicular to the opposing floating trenches.

3. The structure of claim 1 wherein the DMOS transistor comprises at least a row of DMOS transistors, each DMOS transistor comprising a source, a drain, a body region, a gate, and a drift region between the drain and the body region, the gate having a width dimension substantially perpendicular to a row of DMOS transistors, wherein the parallel opposing floating trenches run on opposite sides of each row, there being at least a portion of a row of DMOS transistors between a pair of opposing floating trenches, with the gate width dimension substantially perpendicular to the opposing floating trenches.

4. The structure of claim 1 wherein the drain is a heavily doped region of a first conductivity type, the drain being formed in a lighter doped well region of the first conductivity type, the source, drain, well region, and body region being formed in an epitaxial layer of the first conductivity type.

5. The structure of claim 4 wherein the drift region comprises a portion of the epitaxial layer under the gate.

6. The structure of claim 5 wherein the parallel opposing floating trenches completely deplete the epitaxial region under the gate.

7. The structure of claim 4 further comprising a thick field oxide region between the gate and the well region.

8. The structure of claim 1 wherein the DMOS transistor is a lateral DMOS transistor.

9. The structure of claim 1 wherein the DMOS transistor is a vertical DMOS transistor.

10. The structure of claim 1 wherein each trench comprises an oxide liner and is at least partially filled with polysilicon.

11. The structure of claim 1 wherein the source and drain are regions of a first conductivity type, and the body region is of a second conductivity type, the structure further comprising an epitaxial layer of a first conductivity type in which is formed the source, drain, and body region, and further comprising a substrate of the second conductivity type and a highly doped buried layer of the first conductivity type between the substrate and the epitaxial layer.

12. The structure of claim 11 wherein each trench comprises an oxide liner and is at least partially filled with polysilicon, wherein the polysilicon extends into the substrate.

13. The structure of claim 11 wherein each trench comprises an oxide liner and is at least partially filled with polysilicon, wherein the polysilicon does not extend into the substrate, the structure further comprising a substrate contact extending from the substrate to a surface of the structure running between two parallel trenches to cause a potential on the trenches to be lowered in order to create a space charge region in the drift region by each opposing floating trench that merges under the gate.

14. The structure of claim 11 wherein the parallel opposing floating trenches cause the space charge region to be at least 50% of the epitaxial region between parallel opposing floating trenches.

15. The structure of claim 1 wherein the source is a region of a first conductivity type and the body region is of a second conductivity type, the structure further comprising a deep highly doped region of the second conductivity type extending completely through the body region for lowering a gain of a lateral parasitic bipolar transistor.

16. The structure of claim 1 wherein a spacing of the parallel opposing floating trenches is set to create a space charge region (SCR) in the drift region by each opposing floating trench that merges under the gate at a drain bias voltage that is at or below a maximum rated voltage for the DMOS transistor.

17. A method comprising:

providing a transistor structure having at least one row of DMOS transistors, each DMOS transistor comprising a source, a drain, a body region, a gate, and a drift region between the drain and the body region, the gate having a width dimension substantially perpendicular to the at least one row of DMOS transistors, the transistor structure also having parallel opposing floating trenches, containing a conductive or semiconductor material, running along the at least one row of DMOS transistors, there being at least a portion of the at least one row of DMOS transistors between a pair of opposing floating trenches, with the gate width dimension substantially perpendicular to the opposing floating trenches; and

applying a bias voltage to the drain such that a potential is capacitively coupled to the opposing floating trenches, the potential being lower than the drain voltage, each opposing floating trench creating a space charge region (SCR) in the drift region that merges under the gate.

18. The method of claim 17 wherein the at least one row of DMOS transistors comprises a two-dimensional array of DMOS transistors arranged in rows.

19. The method of claim 17 wherein the drain is a heavily doped region of a first conductivity type, the drain being formed in a lighter doped well region of the first conductivity type, the source, drain, well region, and body region being formed in an epitaxial layer of the first conductivity type.

20. The method of claim 19 wherein the drift region comprises a portion of the epitaxial layer under the gate.

21. The structure of claim 20 wherein the parallel opposing floating trenches completely deplete the epitaxial region under the gate.

22. The method of claim 20 wherein the parallel opposing floating trenches cause the space charge region to be at least 50% of the epitaxial region between parallel opposing floating trenches.

23. The method of claim 17 wherein the DMOS transistor is a lateral DMOS transistor.

24. The method of claim 17 wherein the DMOS transistor is a vertical DMOS transistor.

25. The method of claim 17 wherein a spacing of the parallel opposing floating trenches is set to create a space charge region (SCR) in the drift region by each opposing floating trench that merges under the gate at a drain bias voltage that is at or below a maximum rated voltage for the DMOS transistor.