Memory device and method of manufacturing the device by simultaneously conditioning transition metal oxide layers in a plurality of memory cells
First Claim
1. An integrated circuit structure comprising:
- a single memory cell comprising;
a memory element having a first top electrical contact and a first bottom surface, wherein said memory element comprises;
a first conductive layer;
a bi-stable layer on said first conductive layer; and
a second conductive layer on said bi-stable layer; and
a conductive section having a second top electrical contact and a second bottom surface and comprising a conductive material;
wherein said conductive section is parallel to said memory element and wherein said bottom surface of said memory element is electrically connected to said bottom surface of said conductive section.
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Accused Products
Abstract
Disclosed are non-volatile memory devices that incorporate a series of single or double memory cells. The single memory cells are essentially “U” shaped. The double memory cells comprise two essentially “U” shaped memory cells. Each memory cell comprises a memory element having a bi-stable layer sandwiched between two conductive layers. A temporary conductor may be applied to a series of cells and used to bulk condition the bi-stable layers of the cells. Also, due to the “U” shape of the cells, a cross point wire array may be used to connect a series of cells. The cross point wire array allows the memory elements of each cell to be individually identified and addressed for storing information and also allows for the information stored in the memory elements in all of the cells in the series to be simultaneously erased using a block erase process.
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Citations
25 Claims
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1. An integrated circuit structure comprising:
a single memory cell comprising;
a memory element having a first top electrical contact and a first bottom surface, wherein said memory element comprises;
a first conductive layer;
a bi-stable layer on said first conductive layer; and
a second conductive layer on said bi-stable layer; and
a conductive section having a second top electrical contact and a second bottom surface and comprising a conductive material;
wherein said conductive section is parallel to said memory element and wherein said bottom surface of said memory element is electrically connected to said bottom surface of said conductive section.- View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An integrated circuit structure comprising:
a double memory cell comprising;
a first memory element having a first top electrical contact and a first bottom surface;
a second memory element parallel to said first memory element and having a second top electrical contact and a second bottom surface;
wherein said first memory element and said second memory element each comprise;
a first conductive layer;
a bi-stable layer on said first conductive layer; and
a second conductive layer on said bi-stable layer; and
a conductive section having a third top electrical contact and a third bottom surface and comprising a conductive material;
wherein said conductive section is parallel to and disposed between said first memory element and said second memory element and wherein said third bottom surface is electrically connected to said first bottom surface and said second bottom surface.- View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A method of forming a memory device, said method comprising:
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simultaneously forming a series of single memory cells, wherein forming of each of said single memory cells in said series comprises;
forming two parallel holes in an insulating layer;
forming a memory element with a first top electrical contact in one of said two parallel holes by filling said one of said two parallel holes with a first conductive layer, a transition metal oxide layer on said first conductive layer, and a second conductive layer on said transition metal oxide layer, forming a conductive section with a second top electrical contact in another of said two parallel holes by filling said other of said two parallel holes with a conductive material; and
electrically connecting said memory element and said conductive section;
simultaneously conditioning all of said transition metal oxide layers of said memory elements of said single memory cells in said series, wherein said conditioning causes said transition metal oxide layers to exhibit a bi-stable electrical resistance. - View Dependent Claims (18, 19, 20, 21)
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22. A method of forming a memory device, said method comprising:
simultaneously forming a series of double memory cells, wherein forming of each of said double memory cells in said series comprises;
forming three parallel holes in an insulator layer;
forming a first memory element with a first top electrical contact and a second memory element with a second top electrical contact in two of said three parallel holes by filling said two of said three parallel holes with a first conductive layer, a transition metal oxide layer on said first conductive layer, and a second conductive layer on said transition metal oxide layer, forming a conductive section with a third top electrical contact in another of said three parallel holes by filling said other of said three parallel holes with a conductive material; and
electrically connecting said conductive section to each of said first memory element and said second memory element;
simultaneously conditioning said transition metal oxide layer of said first memory element of each of said double memory cells in said series; and
simultaneously conditioning said transition metal oxide layer of said second memory element of each of said double memory cells in said series, wherein said conditioning causes said transition metal oxide layers to exhibit a bi-stable electrical resistance. - View Dependent Claims (23, 24, 25)
Specification