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Memory device and method of manufacturing the device by simultaneously conditioning transition metal oxide layers in a plurality of memory cells

  • US 20060267086A1
  • Filed: 05/31/2005
  • Published: 11/30/2006
  • Est. Priority Date: 05/31/2005
  • Status: Active Grant
First Claim
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1. An integrated circuit structure comprising:

  • a single memory cell comprising;

    a memory element having a first top electrical contact and a first bottom surface, wherein said memory element comprises;

    a first conductive layer;

    a bi-stable layer on said first conductive layer; and

    a second conductive layer on said bi-stable layer; and

    a conductive section having a second top electrical contact and a second bottom surface and comprising a conductive material;

    wherein said conductive section is parallel to said memory element and wherein said bottom surface of said memory element is electrically connected to said bottom surface of said conductive section.

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