Structure and method for forming a minimum pitch trench-gate FET with heavy body region

• US 20060267088A1
• Filed: 05/26/2005
• Published: 11/30/2006
• Est. Priority Date: 05/26/2005
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Sharp, Joelle, Madson, Gordon K.
• Granted Patent: US 7,553,740 B2
• Time in Patent Office: Days
• US Class Current: 257/341
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode

Abstract

A field effect transistor is formed as follows. Openings are formed in a masking layer extending over a surface of a silicon region. A trench is formed in the silicon region through each opening in the masking layer. A layer of silicon is formed along sidewalls and bottom of each trench and along masking layer sidewalls which define each opening. The masking layer is removed to expose surface areas of the silicon region underlying the masking layer and to expose sidewalls of the layer of silicon to thereby form contact openings over the surface of the silicon region. A contact layer is formed to electrically contact the exposed surface areas of the silicon region and the exposed sidewalls of the layer of silicon.

Claims

1. A method of forming a field effect transistor, comprising:

forming openings in a masking layer extending over a surface of a silicon region;

forming a trench in the silicon region through each opening in the masking layer;

forming a layer of silicon along sidewalls and bottom of each trench and along masking layer sidewalls which define each opening;

removing the masking layer to expose surface areas of the silicon region underlying the masking layer and to expose sidewalls of the layer of silicon to thereby form contact openings over the surface of the silicon region; and

forming a contact layer to electrically contact the exposed surface areas of the silicon region and the exposed sidewalls of the layer of silicon.

2. The method of claim 1 wherein the masking layer comprises a composite layer of oxide-nitride-oxide (ONO).

3. The method of claim 1 further comprising:

forming source regions extending into the silicon layer by implanting impurities at an angle greater than 20°

from the dimension parallel to trench sidewalls.

4. The method of claim 1 wherein the layer of silicon is formed using a selective epitaxial growth (SEG) process.

5. The method of claim 1 wherein the masking layer includes a nitride layer, the method further comprising:

forming a gate dielectric and a recessed gate electrode in each trench;

forming a layer of dielectric over the trenches and the masking layer;

etching the layer of dielectric until the nitride layer in the masking layer is exposed; and

after the step of removing the masking layer, implanting dopants to form a heavy body region in the silicon region between adjacent trenches.

6. The method of claim 1 wherein the layer of silicon is undoped upon formation.

7. The method of claim 1 wherein the silicon region comprises a substrate of a first conductivity type and an epitaxial layer of the first conductivity type extending over the substrate, the method further comprising:

prior to forming the trenches, forming a body region of the second conductivity type in the epitaxial layer, wherein the trenches are formed to extend through the body region and into the epitaxial layer, the layer of silicon being formed to have a doping concentration such that upon substantial formation of the field effect transistor a portion of the layer of silicon extending along the bottom of each trench is of the first conductivity type and portions of the layer of silicon extending along sidewalls of each trench are of the second conductivity type.

8. A method of forming a field effect transistor, comprising:

forming openings in a making layer extending over a surface of a silicon region;

forming a trench in the silicon region through each opening in the masking layer;

forming a layer of silicon along sidewalls and bottom of each trench and along masking layer sidewalls which define the openings in the masking layer; and

removing the masking layer to thereby form contact openings over the surface of the silicon region, the contact openings being defined by exposed sidewalls of the layer of silicon.

9. The method of claim 8, wherein the masking layer comprises an oxide-nitride-oxide composite layer.

10. The method of claim 8 wherein the masking layer includes a nitride layer, the method further comprising:

forming a gate dielectric and a recessed gate electrode in each trench;

forming a layer of dielectric over the trenches and the masking layer;

etching the layer of dielectric until the nitride layer in the masking layer is exposed; and

after removing the masking layer, implanting dopants through the contact openings to form a heavy body region in the silicon region between adjacent trenches.

11. The method of claim 8 further comprising:

forming source regions extending into the silicon layer by implanting impurities at an angle greater than 20°

from the dimension parallel to trench sidewalls.

12. The method of claim 11 wherein the silicon region comprises a substrate of a first conductivity type and an epitaxial layer of the first conductivity type extending over the substrate, the method further comprising:

prior to forming the trenches, forming a body region of the second conductivity type in the epitaxial layer, wherein the trenches are formed to extend through the body region and into the epitaxial layer, the layer of silicon being formed to have a doping concentration such that upon substantial formation of the field effect transistor a portion of the layer of silicon extending along the bottom of each trench is of the first conductivity type and portions of the layer of silicon extending along sidewalls of each trench are of the second conductivity type.

13. A method of forming a field effect transistor, comprising:

forming trenches in a silicon region using a masking layer, the trenches extending from a surface of the silicon region to a predetermined depth in the silicon region;

removing portions of the masking layer to expose surface areas of the silicon region adjacent each trench;

forming a layer of silicon along sidewalls and bottom of each trench, the layer of silicon extending out of each trench and over the exposed surface areas of the silicon region adjacent each trench, the layer of silicon abutting sidewalls of the masking layer remaining after the removing step; and

removing the remaining masking layer to thereby form contact openings over the surface of the silicon region, the contact openings being defined by exposed sidewalls of the layer of silicon.

14. The method of claim 13 wherein the masking layer comprises oxide.

15. The method of claim 13 further comprising:

forming source regions extending into the silicon layer by implanting impurities at an angle greater than 20°

from the dimension parallel to trench sidewalls.

16. The method of claim 13 wherein the layer of silicon is formed using a selective epitaxial growth (SEG) process.

17. The method of claim 13 further comprising:

forming a gate dielectric and a recessed gate electrode in each trench;

after the step of removing the remaining masking layer, forming a layer of dielectric over the trenches and the contact openings;

removing portions of the layer of dielectric from over the contact openings; and

implanting dopants through the contact openings to form heavy body regions in the silicon region.

18. The method of claim 13 wherein the silicon region comprises a substrate of a first conductivity type and an epitaxial layer of the first conductivity type extending over the substrate, the method further comprising:

prior to forming the trenches, forming a body region of the second conductivity type in the epitaxial layer, wherein the trenches are formed to extend through the body region and into the epitaxial layer, the layer of silicon being formed to have a doping concentration such that upon substantial formation of the field effect transistor a portion of the layer of silicon extending along the bottom of each trench is of the first conductivity type and portions of the layer of silicon extending along sidewalls of each trench are of the second conductivity type.

19. A method of forming a field effect transistor, comprising:

forming a pair of trenches in a silicon region;

forming a layer of silicon extending along sidewalls and bottom of each trench, the layer of silicon further extending out of each trench but being discontinuous over a surface of the silicon region so as to form a contact opening over the surface of the silicon region between the pair of trenches; and

through the contact opening, forming a heavy body region in the silicon region between the pair of trenches.

20. The method of claim 19 further comprising:

forming source regions extending into the silicon layer by implanting impurities at an angle greater than 20°

from the dimension parallel to trench sidewalls.

21. The method of claim 20 wherein the silicon region comprises a substrate of the first conductivity type and an epitaxial layer of the first conductivity type extending over the substrate, the method further comprising:

prior to forming the trenches, forming a body region of the second conductivity type in the epitaxial layer, wherein the trenches are formed to extend through the body region and into the epitaxial layer, the layer of silicon being formed to have a doping concentration such that upon substantial formation of the field effect transistor a portion of the layer of silicon extending along the bottom of each trench is of the first conductivity type and portions of the layer of silicon extending along sidewalls of each trench are of the second conductivity type.

22. A field effect transistor comprising:

a pair of trenches in a silicon region; and

a layer of silicon extending along the sidewalls and bottom of each trench, the layer of silicon extending out of each trench but being discontinuous over a surface of the silicon region so as to form a contact opening over the surface of the silicon region between the pair of trenches.

23. The field effect transistor of claim 22 further comprising:

a gate dielectric layer lining sidewalls and bottom of the layer of silicon in each trench;

a gate electrode over the gate dielectric in each trench; and

source regions of a first conductivity type flanking each side of the gate electrode in each trench, wherein at least a portion of each source region is formed in the layer of silicon such that sidewalls of adjacent source regions define the contact opening.

24. The field effect transistor of claim 22 wherein the silicon region comprises:

a substrate of the first conductivity type;

an epitaxial layer of the first conductivity type extending over the substrate; and

a body region of the second conductivity type in the epitaxial layer, wherein the pair of trenches extend through the body region and into the epitaxial layer.

25. The field effect transistor of claim 24 wherein a portion of the layer of silicon extending along the bottom of each trench is of the first conductivity type, and portions of the layer of silicon extending along sidewalls of each trench are of the second conductivity type.

26. The field effect transistor of claim 22 further comprising:

a heavy body region in the silicon region directly below the contact opening, the heavy body region being self-aligned to the pair of trenches.

27. The field effect transistor of claim 22 further comprising a contact layer electrically contacting sidewalls of the layer of silicon and a surface of the silicon region defined by the contact opening.

28. A field effect transistor comprising:

a plurality of trenches in a silicon region;

a layer of silicon lining sidewalls and bottom of each trench, the layer of silicon extending out of each trench but being discontinuous over a surface of the silicon region so as to form a contact opening over the surface of the silicon region between adjacent trenches;

a gate dielectric layer lining sidewalls and bottom of the layer of silicon in each trench;

a gate electrode over the gate dielectric in each trench; and

source regions of a first conductivity type extending into the layer of silicon.

29. The field effect transistor of claim 28 wherein sidewalls of adjacent source regions define the contact openings.

30. The field effect transistor of claim 28 wherein the silicon region comprises:

a substrate of the first conductivity type;

an epitaxial layer of the first conductivity type extending over the substrate;

a body region of the second conductivity type in the epitaxial layer, wherein the plurality of trenches extend through the body region and into the epitaxial layer.

31. The field effect transistor of claim 28 further comprising:

a heavy body region of a second conductivity type in the silicon region directly below each contact opening, the heavy body regions being self-aligned to the plurality of trenches.

32. The field effect transistor of claim 31 further comprising a contact layer electrically contacting the heavy body regions and sidewalls of the layer of silicon.