Trenched-gate field effect transistors and methods of forming the same

• US 20060267090A1
• Filed: 04/04/2006
• Published: 11/30/2006
• Est. Priority Date: 04/06/2005
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Yilmaz, Hamza, Calafut, Daniel, Rexer, Christopher Lawrence, Sapp, Steven
• Granted Patent: US 7,504,306 B2
• Time in Patent Office: Days
• US Class Current: 257/341
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A monolithically integrated field effect transistor and Schottky diode includes gate trenches extending into a semiconductor region. Source regions having a substantially triangular shape flank each side of the gate trenches. A contact opening extends into the semiconductor region between adjacent gate trenches. A conductor layer fills the contact opening to electrically contact: (a) the source regions along at least a portion of a slanted sidewall of each source region, and (b) the semiconductor region along a bottom portion of the contact opening, wherein the conductor layer forms a Schottky contact with the semiconductor region.

Claims

1-73. -73. (canceled)

74. A method of forming a field effect transistor comprising an active area and a termination region surrounding the active area, the method comprising:

forming gate trenches extending into a silicon region of a first conductivity type;

forming a well region of a second conductivity type in the silicon region;

forming a recessed gate in each gate trench;

forming a dielectric cap over each gate;

recessing all exposed surfaces of the well region to form a recess in the well region between every two adjacent trenches such that the recess has sloped walls and a bottom located between a top surface of the dielectric cap and a top surface of the recessed gate; and

without masking any portion of the active area, performing a zero-degree blanket implant to form a heavy body region of the second conductivity type in the well region between every two adjacent trenches whereby the heavy body region is self-aligned to the gate trenches.

75. The method of claim 74 further comprising performing a two-pass angled implant into the sloped walls of each recess to thereby form source regions of the first conductivity type adjacent the dielectric cap, the sloped walls of the recess forming an outer wall of each source region, the source regions being self-aligned to the trenches.

76. The method of claim 75 further comprising forming a source conductor contacting the outer wall of each source region and contacting the heavy body region along the bottom of the recess.

77. The method of claim 74 further comprising:

forming a wide trench in the termination region; and

filling the wide trench with LOCOS.

78. The method of claim 74 further comprising forming a surface gate in the termination region simultaneously with forming the recessed gate in the gate trenches.

79. The method of claim 78 further comprising:

forming an opening over the surface gate; and

forming a gate conductor contacting the surface gate through the opening.

80. The method of claim 74 further comprising:

forming a termination trench in the termination region simultaneously with forming the gate trenches;

forming a recessed gate in the termination trench simultaneously with forming the recessed gate in the gate trenches;

forming an opening over the recessed gate in the termination trench; and

forming a gate conductor contacting the recessed gate in the termination trench through the opening.

81. The method of claim 78 further comprising:

forming an opening over the surface gate; and

simultaneously with recessing all exposed surfaces of the well region, recessing the surface gate through the opening to thereby expose sidewalls of the surface gate through the opening; and

filling the opening with a gate conductor, the gate conductor contacting the surface gate along the exposed sidewalls of the surface gate.

82. The method of claim 74 further comprising:

simultaneously with forming the gate trenches, forming a wide trench in the termination region; and

filling a bottom portion of the wide trench and each gate trench with LOCOS.

83. The method of claim 82 further comprising forming a termination gate simultaneously with forming the recessed gate in the gate trenches, the termination gate extending in part inside the wide trench and in part over a mesa region adjacent the wide trench.

84. The method of claim 83 further comprising:

forming a contact opening over the termination gate in the wide trench; and

simultaneously with recessing all exposed surfaces of the well region, recessing the termination gate through the opening to thereby expose sidewalls of the termination gate through the opening; and

filling the opening with a gate conductor, the gate conductor contacting the exposed sidewalls of the termination gate.

85. The method of claim 74 further comprising:

prior to forming the recessed gate, forming a thick bottom dielectric along a bottom portion of each gate trench; and

prior to forming the recessed gate, forming a gate dielectric lining the sidewalls of each gate trench, wherein the thick bottom dielectric is thicker than the gate dielectric.

86. The method of claim 74 further comprising:

prior to forming the recessed gate, forming a shield electrode along a bottom portion of each gate trench; and

prior to forming the recessed gate, forming a dielectric layer over each shield electrode.

87-108. -108. (canceled)