Semiconductor Device Including Shallow Trench Isolation (STI) Regions with a Superlattice Therebetween

• US 20060267130A1
• Filed: 06/20/2006
• Published: 11/30/2006
• Est. Priority Date: 06/26/2003
• Status: Abandoned Application

• Current Assignee: Mears Technologies Incorporated
• Original Assignee: RJ Mears LLC (Atomera Incorporated)
• Inventors: Rao, Kalipatnam Vivek
• Application Number:
  US11/425,201
• Publication Number:
  US 20060267130A1
• Time in Patent Office: Days
• US Class Current: 257/499
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A semiconductor device may include a semiconductor substrate and a plurality of shallow trench isolation (STI) regions in the substrate. More particularly, at least some of the STI regions may include divots therein. The semiconductor device may further include a respective superlattice between adjacent STI regions, and respective non-monocrystalline stringers in the divots.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a plurality of shallow trench isolation (STI) regions in said substrate, at least some of said STI regions including divots therein;

a respective superlattice between adjacent STI regions; and

respective non-monocrystalline stringers in the divots.

2. The semiconductor device of claim 1 wherein each of said non-monocrystalline stringers comprises a dopant therein.

3. The semiconductor device according to claim 2 wherein said dopant comprises a channel-stop implant dopant.

4. The semiconductor device according to claim 1 further comprising a plurality of NMOS and PMOS transistor channels associated with the superlattices so that the semiconductor device comprises a CMOS semiconductor device.

5. The semiconductor device according to claim 1 wherein each superlattice comprises a plurality of stacked groups of layers with each group comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon, and with the at least one non-semiconductor monolayer being constrained within a crystal lattice of adjacent base semiconductor portions.

6. The semiconductor device according to claim 5 wherein each non-semiconductor layer is a single monolayer thick.

7. The semiconductor device according to claim 5 wherein each base semiconductor portion is less than eight monolayers thick.

8. The semiconductor device according to claim 5 wherein the superlattice further comprises a base semiconductor cap layer on an uppermost group of layers.

9. The semiconductor device according to claim 5 wherein all of the base semiconductor portions are a same number of monolayers thick.

10. The semiconductor device according to claim 5 wherein at least some of the base semiconductor portions are a different number of monolayers thick.

11. The semiconductor device according to claim 5 wherein all of the base semiconductor portions are a different number of monolayers thick.

12. The semiconductor device according to claim 5 wherein each base semiconductor portion comprises a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors.

13. The semiconductor device according to claim 5 wherein each non-semiconductor layer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

14. The semiconductor device according to claim 5 wherein opposing base semiconductor portions in adjacent groups of layers are chemically bound together.

15. A semiconductor device comprising:

a semiconductor substrate;

a plurality of shallow trench isolation (STI) regions in said substrate, at least some of said STI regions including divots therein;

a respective superlattice between adjacent STI regions, each superlattice comprising a plurality of stacked groups of layers with each group comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon, and with the at least one non-semiconductor monolayer being constrained within a crystal lattice of adjacent base semiconductor portions;

respective non-monocrystalline stringers in the divots; and

a plurality of NMOS and PMOS transistor channels associated with the superlattices so that the semiconductor device comprises a CMOS semiconductor device.

16. The semiconductor device according to claim 15 wherein each of said non-monocrystalline stringers comprises a dopant therein.

17. The semiconductor device according to claim 16 wherein said dopant comprises a channel-stop implant dopant.

18. The semiconductor device according to claim 15 wherein each non-semiconductor layer is a single monolayer thick.

19. The semiconductor device according to claim 15 wherein each base semiconductor portion is less than eight monolayers thick.

20. The semiconductor device according to claim 15 wherein the superlattice further comprises a base semiconductor cap layer on an uppermost group of layers.

21. The semiconductor device according to claim 15 wherein each base semiconductor portion comprises a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors;

and wherein each non-semiconductor layer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.