Integrated circuit package with air gap

• US 20060267194A1
• Filed: 07/14/2006
• Published: 11/30/2006
• Est. Priority Date: 10/15/2002
• Status: Abandoned Application

• Current Assignee: Sehat Sutardja
• Original Assignee: Sehat Sutardja
• Inventors: Sutardja, Sehat
• Application Number:
  US11/486,557
• Publication Number:
  US 20060267194A1
• Time in Patent Office: Days
• US Class Current: 257/729
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/315 the encapsulation having a cavity
• CPC Class Codes: H01L 23/345 Arrangements for heating thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/30107 Inductance
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H03B 5/04 Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
• CPC Class Codes: H03B 5/36 active element in amplifier being semiconductor device H03B5/323, H03B5/326 , H03B5/38 take precedence
• CPC Class Codes: H03L 1/026 by using a memory for digitally storing correction values H03L1/025 takes precedence
• CPC Class Codes: H03L 1/027 by using frequency conversion means which is variable with temperature, e.g. mixer, frequency divider, pulse add/substract logic circuit H03L1/023, H03L1/026 take precedence
• CPC Class Codes: H03L 1/04 Constructional details for maintaining temperature constant
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/099 : concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/1976 : using a phase accumulator for controlling the counter or frequency divider

Abstract

An integrated circuit (IC) package comprises an IC wafer. A first portion is arranged adjacent to the IC wafer. A second portion is arranged adjacent to the IC wafer and that is spaced from the first portion. The first and second portions comprise at least one of annealed glass paste (AGP) and epoxy. A layer is arranged adjacent to the first and second portions and creates an air gap between the layer, the first and second portions and the IC wafer.

Claims

1. An integrated circuit (IC) package, comprising:

an IC wafer; and

a first portion that is arranged adjacent to said IC wafer;

a second portion that is arranged adjacent to said IC wafer and that is spaced from said first portion, wherein said first and second portions comprise at least one of annealed glass paste (AGP) and epoxy; and

a layer that is arranged adjacent to said first and second portions and that creates an air gap between said layer, said first and second portions and said IC wafer.

2. The IC package of claim 1 wherein said IC wafer comprises a silicon wafer.

3. The IC package of claim 1 further comprising a molding material that encapsulates at least part of said IC wafer, said layer and said first and second portions.

4. The IC package of claim 1 wherein said layer comprises at least one of glass and silicon.

5. The IC package of claim 1 further comprising a conductive material that is arranged adjacent to said first and second portions.

6. The IC package of claim 2 wherein said silicon wafer comprises a circuit component, wherein said air gap is arranged between said circuit component, said layer and said first and second portions.

7. The IC package of claim 6 wherein said circuit component comprises at least one of an oscillator and an inductor.

8. The IC package of claim 7 wherein said inductor comprises a spiral inductor.

9. The IC package of claim 1 wherein said first and second portions comprises glass frit.

10. The IC package of claim 1 wherein said first and second portions are applied to said silicon wafer using one of a screen printing, dipping and masking.

11. The IC package of claim 5 wherein said conductive material comprises one of a conductive epoxy and a conductive epoxy paint.

12. The IC package of claim 5 wherein said conductive material is applied to said first and second portions by dipping said at least part of said IC package in a container containing said conductive material.

13. The IC package of claim 1 wherein said layer has a first width that is less than a second width of said silicon wafer.

14. The IC package of claim 1 wherein said IC wafer comprises bond pads.

15. The IC package of claim 1 wherein said layer has a first width that is less than a second width of said silicon wafer and further comprising bond pads that are located in an outer region of said silicon wafer.

16. A method of providing an integrated circuit (IC) package, comprising:

providing an IC wafer; and

arranging a first portion adjacent to said IC wafer;

arranging a second portion adjacent to said IC wafer and spaced from said first portion, wherein said first and second portions comprise at least one of annealed glass paste (AGP) and epoxy; and

arranging a layer adjacent to said first and second portions, wherein said layer creates an air gap between said layer, said first and second portions and said IC wafer.

17. The method of claim 16 wherein said IC wafer comprises a silicon wafer.

18. The method of claim 16 further comprising encapsulating at least part of said IC wafer, said layer and said first and second portions.

19. The method of claim 16 wherein said layer comprises at least one of glass and silicon.

20. The method of claim 16 further comprising arranging a conductive material adjacent to said first and second portions.

21. The method of claim 16 further comprising arranging said air gap between said circuit component, said layer and said first and second portions.

22. The method of claim 21 wherein said circuit component comprises at least one of an oscillator and an inductor.

23. The method of claim 22 wherein said inductor comprises a spiral inductor.

24. The method of claim 16 wherein said first and second portions comprise glass frit.

25. The method of claim 16 further comprising applying said first and second portions to said silicon wafer using one of a screen printing, dipping and masking.

26. The method of claim 20 wherein said conductive material comprises one of a conductive epoxy and a conductive epoxy paint.

27. The method of claim 16 wherein said layer has a first width that is less than a second width of said silicon wafer.

28. The method of claim 16 further comprising providing bond pads on said IC wafer in an outer region of said silicon wafer.