Nonvolatile semiconductor static random access memory device

• US 20060268615A1
• Filed: 12/08/2005
• Published: 11/30/2006
• Est. Priority Date: 05/30/2005
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Kang, Hee Bok, Ahn, Jin Hong
• Granted Patent: US 7,307,872 B2
• Time in Patent Office: Days
• US Class Current: 365/185.180
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down

Abstract

A nonvolatile semiconductor memory device obtained by combining a nonvolatile memory device with a SRAM is provided to improve operating speed and reliability. The nonvolatile semiconductor memory device includes a plurality of data registers. Preferably, each of the plurality of data registers includes a pull-up driving unit adapted and configured to pull up a storage node, a pull-down driving unit adapted and configured to pull down the storage node, a data input/output unit adapted and configured to selectively input and output data between a bit line and the storage node depending on a voltage applied to a word line, and a data storing unit adapted and configured to store data of the storage node depending on a voltage applied to a top word line and a bottom word line or to output the stored data to the storage node.

Claims

1. A nonvolatile semiconductor memory device including a plurality of data registers,

wherein each of the plurality of data registers comprises:

a storage node;

a pull-up driving unit adapted and configured to pull up the storage node;

a pull-down driving unit adapted and configured to pull down the storage node;

a data input/output unit adapted and configured to selectively input and output data between a bit line and the storage node depending on a voltage applied to a word line; and

a data storing unit adapted and configured to store data of the storage node depending on a voltage applied to a top word line and a bottom word line or to output the stored data to the storage node.

2. The nonvolatile semiconductor memory device according to claim 1, wherein the data storing unit includes a plurality of nonvolatile memory cells.

3. The nonvolatile semiconductor memory device according to claim 2, wherein each of the plurality of nonvolatile memory cells comprises:

the bottom word line;

a float channel layer formed on the bottom word line;

a ferroelectric layer formed on the float channel layer, and adapted and configured to store data; and

the top word line formed on the ferroelectric layer in parallel with the bottom word line.

4. The nonvolatile semiconductor memory device according to claim 3, wherein the float channel layer is formed of at least one of a carbon nano tube, silicon, germanium and an organic semiconductor.

5. The nonvolatile semiconductor memory device according to claim 3, wherein each of the plurality of nonvolatile memory cells writes data into the ferroelectric layer depending on a level of the top word line while the bottom word line is selected.

6. The nonvolatile semiconductor memory device according to claim 3, wherein each of the plurality of nonvolatile memory cells induces different channel resistances in the float channel layer to read corresponding data depending on a polarization state of charges stored in the ferroelectric layer.

7. The nonvolatile semiconductor memory device according to claim 3, wherein the float channel layer attains a high resistance state to be turned off when the polarization state of charges stored in the ferroelectric layer induces positive charges into the float channel of the float channel layer.

8. The nonvolatile semiconductor memory device according to claim 3, wherein the float channel layer attains a low resistance state to be turned on when the polarization state of charges stored in the ferroelectric layer induces negative charges into the float channel of the float channel layer.

9. The nonvolatile semiconductor memory device according to claim 3, wherein high level data are written in the ferroelectric layer when:

a positive voltage is applied to the bottom word line;

a negative voltage is applied to the top word line; and

a ground voltage is applied to a drain region and a source region.

10. The nonvolatile semiconductor memory device according to claim 9, wherein the polarization state of charges stored in the ferroelectric layer is induces positive charges into the float channel of the float channel layer and high level data are read, when a ground voltage is applied to the bottom word line and the top word line.

11. The nonvolatile semiconductor memory device according to claim 9, wherein a previously stored high level data in the ferroelectric layer is maintained when a positive voltage is applied to the bottom word line and the top word line, a positive voltage is applied to a drain region and a source region.

12. The nonvolatile semiconductor memory device according to claim 3, wherein low level data are written in the ferroelectric layer when a positive voltage is applied to the bottom word line and the top word line and a ground voltage is applied to a drain region and a source region.

13. The nonvolatile semiconductor memory device according to claim 12, wherein the polarization state of charges stored in the ferroelectric layer is induces megative charges into the float channel of the float channel layer and low level data are read, when a ground voltage is applied to the bottom word line and the top word line.

14. The nonvolatile semiconductor memory device according to claim 1, wherein the pull-up driving unit comprises a plurality of PMOS transistors each configured to have a gate cross-coupled to the storage node with a latch type circuit.

15. The nonvolatile semiconductor memory device according to claim 1, wherein the pull-down driving unit comprises a plurality of NMOS transistors each configured to have a gate cross-coupled to the storage node with a latch type circuit.

16. The nonvolatile semiconductor memory device according to claim 1, wherein each of the data input/output units comprises a plurality of switch units each adapted and configured to selectively input and output data between the bit line and the storage node of a corresponding one of the plurality of data registers depending on a voltage applied to the word line.

17. The nonvolatile semiconductor memory device according to claim 16, wherein the switch unit is a NMOS transistor configured to have a gate connected to the word line.

18. The nonvolatile semiconductor memory device according to claim 1, wherein the data stored in the data storing unit of the data register are restored by a program state of the pull-up driving unit at a power-on mode.