Semiconductor substrate, method for fabricating the same, and method for fabricating semiconductor device

• US 20060270193A1
• Filed: 08/10/2006
• Published: 11/30/2006
• Est. Priority Date: 01/20/2003
• Status: Active Grant

• Current Assignee: Panasonic Semiconductor Solutions Co., Ltd. (Winbond Electronics Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Hidaka, Yoshiharu, Ikenouchi, Katsuyuki
• Granted Patent: US 7,393,759 B2
• Time in Patent Office: Days
• US Class Current: 438/459
• CPC Class Codes: H01L 21/02008 Multistep processes
• CPC Class Codes: H01L 21/02024 Mirror polishing
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 2223/54493 Peripheral marks on wafers, e.g. orientation flats, notches, lot number
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

In a semiconductor substrate having a notch in an edge portion thereof, each of the two shoulder portions of the notch is configured as an arc and the difference in curvature between the two shoulder portions of the notch is not less than 0 mm and not more than 0.1 mm.

Claims

1-4. -4. (canceled)

5. A method for fabricating a semiconductor device using a semiconductor substrate in which a notch is formed in an edge portion thereof, the notch has two shoulder portions each configured as an arc, a difference in curvature between the two shoulder portions is not less than 0 mm and not more than 0.1 mm, and each of the two shoulder portions has a curvature not less than 0.3 mm and not more than 2.0 mm, the method comprising the steps of:

burying an insulating film or a conductive film in a depressed portion provided in the semiconductor substrate; and

planarizing the insulating film or the conductive film by chemical mechanical polishing.

6. A method for fabricating a semiconductor device using a semiconductor substrate in which a notch is formed in an edge portion thereof, the notch has two shoulder portions each configured as an arc, a difference in curvature between the two shoulder portions is not less than 0 mm and not more than 0.1 mm, and each of the two shoulder portions has a curvature not less than 0.3 mm and not more than 2.0 mm, the method comprising the steps of:

forming an end-point detection film on the semiconductor substrate;

performing etching with respect to the end-point detection film and the semiconductor substrate by using a mask pattern to form an isolation trench;

burying an insulating film in the isolation trench; and

planarizing the insulating film by chemical mechanical polishing.

7. The method of claim 6, wherein a polishing speed for the insulating film is double or more a polishing speed for the end-point detection film in the step of planarizing the insulating film.

8. The method of claim 6, further comprising, after the step of planarizing the insulating film, the step of:

polishing the end-point detection film by chemical mechanical polishing.

9-12. -12. (canceled)