Integrated RF front end with stacked transistor switch

• US 20060270367A1
• Filed: 08/07/2006
• Published: 11/30/2006
• Est. Priority Date: 06/23/2004
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: James S. Cable, Mark L. Burgener
• Inventors: Burgener, Mark L., Cable, James S.
• Granted Patent: US 8,131,251 B2
• Time in Patent Office: Days
• US Class Current: 455/127.100
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01Q 23/00 Antennas with active circuits or circuit elements integrated within them or attached to them
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 1/565 using inductive elements
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/372 Noise reduction and elimination in amplifier
• CPC Class Codes: H03F 2200/387 A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2200/61 the cascode amplifier has more than one common gate stage
• CPC Class Codes: H03F 3/189 High-frequency amplifiers, e.g. radio frequency amplifiers
• CPC Class Codes: H03F 3/19 with semiconductor devices only
• CPC Class Codes: H03F 3/21 with semiconductor devices only H03F3/245 takes precedence
• CPC Class Codes: H03F 3/2171 with field-effect devices H03F3/2173 - H03F3/2178 take precedence
• CPC Class Codes: H03F 3/68 Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602
• CPC Class Codes: H03G 11/00 Limiting amplitude; Limiting rate of change of amplitude ; Clipping in general
• CPC Class Codes: H03G 3/3042 in modulators, frequency-changers, transmitters or power amplifiers transmission power control in bidirectional transmission systems H04W52/04
• CPC Class Codes: H04B 1/0053 with common antenna for more than one band
• CPC Class Codes: H04B 1/0475 with means for limiting noise, interference or distortion H04B1/0483 takes precedence
• CPC Class Codes: H04B 1/48 : in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter H04B1/46 takes precedence
• CPC Class Codes: H04L 27/04 : Modulator circuits; Transmitter circuits

Abstract

A monolithic integrated circuit (IC), and method of manufacturing same, that includes all RF front end or transceiver elements for a portable communication device, including a power amplifier (PA), a matching, coupling and filtering network, and an antenna switch to couple the conditioned PA signal to an antenna. An output signal sensor senses at least a voltage amplitude of the signal switched by the antenna switch, and signals a PA control circuit to limit PA output power in response to excessive values of sensed output. Stacks of multiple FETs in series to operate as a switching device may be used for implementation of the RF front end, and the method and apparatus of such stacks are claimed as subcombinations. An iClass PA architecture is described that dissipatively terminates unwanted harmonics of the PA output signal. A preferred embodiment of the RF transceiver IC includes two distinct PA circuits, two distinct receive signal amplifier circuits, and a four-way antenna switch to selectably couple a single antenna connection to any one of the four circuits.

Claims

1. An integrated RF Power Amplifier (PA) circuit, comprising:

a) an input node to accept an input signal with respect to a reference voltage Vref, coupled to a gate G1 of a first insulated-gate FET M1;

b) a plurality of additional insulated-gate FETs M2 to Mn having a same polarity as M1 and coupled in series with M1 to form a control circuit configured to control conduction between the reference voltage and an output drive node, wherein FETs M2 to Mn are each enslaved to M1; and

c) an output coupling capacitor coupling the output drive node to an output load node.

2. The integrated circuit of claim 1, further comprising (d) an output power control input node coupled to a power controlling insulated-gate FET that is coupled in series connection with M1.

3. The integrated circuit of claim 2, wherein the power controlling FET is disposed between the reference voltage and a power supply voltage external to the PA.

4. The integrated circuit of claim 2, wherein the power controlling FET is one of the FETs M2 to Mn.

5. The integrated circuit of claim 1, further comprising a low-pass filter disposed in series with the output coupling capacitor between the output drive node and the output load node.

6. An integrated circuit including a multiple-FET stack circuit for controlling conduction between a drive output node Vdrive and a reference voltage node Vref under control of an input signal applied between an input signal node and Vref, the integrated circuit comprising:

a) a series stack of J same-polarity FETs M_N, N an integer between 1 and J and J an integer 3 or greater, each FET M_N having a source S_N, a gate G_N and a drain D_N,

b) an input signal node coupled to the gate G₁ of a signal-input FET M₁ of the FET stack;

c) for 0<

N<

J, a series coupling between each drain D_N and the source S_(N+1) of a next higher FET M_(N+1) of the FET stack;

d) for 1<

N≦

J, a gate coupling between each gate G_N and at least one lower FET <sub>M(N−

K)</sub>, K an integer between 1 and (N−

1), in a configuration enslaving each FET M_(N+1) to M₁ so as to conduct substantially concurrently with, and under control of, conduction in M₁;

e) a source coupling for the FET stack between S₁ and Vref; and

f) a drain coupling for the FET stack between D₁ and Vdrive.

7. The integrated circuit of claim 6, wherein a peak value of voltage on Vdrive with respect to Vref, Vdrive(peak), is divided approximately uniformly across all J FETS such that each drain-source voltage Vds_(N) is approximately Vdrive(peak)/J.

8. The integrated circuit of claim 6, wherein each gate coupling comprises a capacitive coupling between G_N and S₁ for each N, 1<

N≦

J.

9. The integrated circuit of claim 6, further comprising a resistive divider for biasing a FET M_N, N>

1, of the FET stack.

10. A Class A, B or C RF PA comprising an integrated circuit according to claim 6, wherein the multiple-FET stack is configured as a primary amplifying device of the Class A, B or C RF PA.

11. A quad mixer comprising an integrated circuit according to claim 6.

12. A Class F RF PA comprising an integrated circuit according to claim 6, wherein the multiple-FET stack is configured as a primary amplifying device of the Class F RF PA.