Switched Processor Datapath

• US 20060271614A1
• Filed: 07/18/2006
• Published: 11/30/2006
• Est. Priority Date: 08/20/2001
• Status: Active Grant

• Current Assignee: Ricoh Company Limited
• Original Assignee: Ricoh Company Limited
• Inventors: Baxter, Michael A.
• Granted Patent: US 7,616,628 B2
• Time in Patent Office: Days
• US Class Current: 708/490
• CPC Class Codes: H04L 12/5601 Transfer mode dependent, e.g. ATM
• CPC Class Codes: H04L 2012/5678 Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
• CPC Class Codes: H04L 49/1561 Distribute and route fabrics, e.g. Batcher-Banyan
• CPC Class Codes: H04L 49/256 Routing or path finding in ATM switching fabrics

Abstract

Data-processing systems including processor datapaths that efficiently support computationally advantageous routing operations are disclosed. Data-processing methods based on such systems are also disclosed. An exemplary data-processing system includes a register file, a routing unit, a switch, and an arithmetic logic unit. The arithmetic logic unit may include a bitwise function unit, pipeline register, and an accumulator. The switch may have N data inputs and log_M(N) switching stages. M may equal 2 or 4. In the case of log₂(N) stages, each switching stage has N/2 switching cells. The routing unit may include a control logic that generates a control signal, and various logics that respectively operate on various bit groups of the control signal.

Claims

1. A processing system comprising:

a register file having an input and an output;

a data routing unit having an input and an output, the input of the data routing unit coupled to the output of the register file, the data routing unit capable of assembling and selecting a data signal; and

an arithmetic logic unit having an input and an output, the input of the arithmetic logic unit coupled to the output of the data routing unit and the output of the arithmetic logic unit coupled to the input of the register file.

2. The processing system of claim 1 wherein the data routing unit is adapted to assemble a data signal, control information pathways and perform routing functions on the data signal.

3. The processing system of claim 2 wherein the data routing unit further comprises:

a switch coupled to the output of the routing unit, the switch capable of controlling information pathways and performing routing functions on the data signal.

4. The processing system of claim 3 wherein the switch is a Banyan switch.

5. The processing system of claim 4 wherein the Banyan switch comprises N data inputs, and log_M(N) switching stages.

6. The processing system of claim 5 wherein M is selected from a group comprising 2 and 4.

7. The processing system of claim 1 wherein the arithmetic logic unit comprises:

a bitwise function unit having an input and an output, the input of the bitwise function unit coupled to the output of the data routing unit;

a pipeline register having an input and an output, the input of the pipeline register coupled to the output of the bitwise function unit; and

an accumulator having an input and an output, the input of the accumulator coupled to the output of the pipeline register and the output of the accumulator coupled to the input of the register file.

8. The processing system of claim 1 wherein the data routing unit comprises:

a routing unit having an input and an output, the input of the routing unit coupled to the output of the register file;

a switch having an input and an output, the input of the switch coupled to an output of the routing unit, the output of the switch coupled to the input of the arithmetic logic unit.

9. The processing system of claim 3 further comprising a switch control unit having an input and an output, the output of the switch control unit coupled to a second input of the switch.

10. The processing system of claim 2 further comprising a constant generator having an input and an output, the output of the constant generator coupled to a second input of the routing unit.

11. The processing system of claim 2 wherein the routing unit comprises:

a control logic generating a control signal having groups of bits; and

a plurality of logics respectively operating on the groups of bits.

12. The processing system of claim 9 wherein the switch control unit comprises:

a shift constants generator having an input and an output, the input of the shift constants generator coupled to the input of the switch control unit;

a pipeline flip-flop having an input and an output, the input of the pipeline flip-flop coupled to the output of the shift constants generator; and

a switch tree having an input and an output, the input of the switch tree coupled to the output of the pipeline flip-flop, and the output of the switch tree forming the output of the switch control unit.

13. A computer-implemented method of processing data for use with a system for routing and manipulating data, the method comprising:

receiving data;

selectively assembling and routing the data using a data routing unit; and

performing arithmetic or logic functions on the data.

14. The method of claim 13 wherein selectively assembling the data comprises selectively aligning and transferring the data.

15. The method of claim 14 wherein a routing unit selectively aligns and transfers the data and a switch selectively routes the data.

16. The method of claim 15 wherein the switch is a Banyan switch.

17. The method of claim 15 wherein selectively routing the data includes performing bitfield manipulation operations on the data.

18. The method of claim 15 wherein selectively routing the data includes shifting or rotating the data.

19. The method of claim 16 wherein selectively routing the data comprises:

receiving N data inputs; and

routing the N data inputs in log_M(N) switching stages, where M is 2 or 4.

20. The method of claim 19 wherein the stages have N/2 cells, the cells capable of transferring a data input from any input of the cell to any output of the cell.

21. The method of claim 15 wherein selectively aligning and transferring the data comprises:

generating a routing control signal having groups of bits; and

operating on the groups of bits to control the aligning and transferring.

22. The method of claim 15 wherein selectively aligning and transferring the data comprises transferring conjoined data, transferring a shifted positive constant, transferring a shifted two'"'"'s-complemented constant, conjoining flag bits, transferring a sign-extended constant, or transferring a shifted signal.

23. The method of claim 15 further comprising generating a switching control signal that specifies a routing operation or bitfield manipulation operation.

24. The method of claim 23 wherein the routing operation or bitfield manipulation operation comprises a circular shift operation, a logical shift operation, or a data alignment.

25. The method of claim 23 wherein generating a switching control signal comprises:

receiving an input code;

outputting a shift code derived from the input code; and

generating and outputting the switching control signal in response to the shift code.

26. The method of claim 25 wherein the input code is a Rotate Left Circular (RLC) code.

27. The method of claim 26 wherein the shift code is the RLC code, an inverted RLC code, a zoned RLC code, or a fixed RLC code.

28. The method of claim 27 wherein the zoned RLC code includes a bit position shift indication.

29. The method of claim 15 further comprising selectively generating and outputting constants or bitfield mask primitives.

31. The processing system of claim 29 wherein means for selectively assembling the data comprises means for selectively aligning and transferring the data.

32. The processing system of claim 31 wherein a routing unit selectively aligns and transfers the data and a switch selectively routes the data.

33. The processing system of claim 32 wherein the switch is a Banyan switch.

34. The processing system of claim 33 wherein the Banyan switch comprises N stages for routing the data, the N stages each having N/2 means for transferring a signal from any input to any output.

35. The processing system of claim 33 further comprising means for generating a switching control signal that specifies a routing operation or bitfield manipulation operation, the means for generating a switching control signal coupled to the Banyan switch.

36. The processing system of claim 35 wherein the routing operation or bitfield manipulation operation comprises a circular shift operation, a logical shift operation, or a data alignment.

37. The processing system of claim 35 wherein the means for generating a switching control signal comprises:

means for receiving an input code;

means for outputting a shift code derived from the input code; and

means for generating and outputting the switching control signal in response to the shift code.

30. A processing system comprising:

means for receiving data;

means for selectively assembling and routing the data using a data routing unit; and

means for performing arithmetic or logic functions on the data.