System and method for transmitting data packets in a computer system having a memory hub architecture
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Accused Products
Abstract
A system and method for transmitting data packets from a memory hub to a memory controller is disclosed. The system includes an upstream reception port coupled an upstream link. The upstream reception port receives the data packets from downstream memory hubs. The system further includes a bypass bus coupled to the upstream reception port. The bypass bus transports the data packets from the upstream reception port. The system further includes a temporary storage coupled to the upstream reception port and configured to receive the data packets from the upstream reception port. The system further includes a bypass multiplexer for selectively coupling an upstream transmission port to either one of a core logic circuit, the temporary storage, or the bypass bus. The system further includes a breakpoint logic circuit coupled to the bypass multiplexer and configured to switch the bypass multiplexer to selectively connect the upstream transmission port to either one of the core logic circuit, the bypass bus, or the temporary storage. The system further includes a local memory coupled to the core logic circuit and operable to receive and send the data packets to the core logic circuit.
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Citations
72 Claims
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1-42. -42. (canceled)
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43. A memory hub operable to control communications for an upstream link, the memory hub comprising:
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a transmission port operable to transmit data to the upstream link;
a reception port operable to receive first data for the upstream link;
core logic operable to receive local data for the upstream link;
a bypass multiplexer coupled to the transmission port, the reception port, and the core logic, the bypass multiplexer operable to selectively couple the upstream link to the reception port or the core logic; and
breakpoint logic coupled to the bypass multiplexer operable to identify a breakpoint and, responsive to the identification, operable to couple a control signal to the bypass multiplexer to initiate a switch between the reception port and the core logic. - View Dependent Claims (44, 45, 46, 47, 48, 49, 50, 51, 52)
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53. A memory system comprising:
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a memory controller;
a memory hub coupled to the controller by an upstream link, the memory hub operable to control communications for the upstream link, the memory hub comprising;
a transmission port coupled to the upstream link;
a reception port operable to receive first data for the upstream link;
core logic operable to receive local data for the upstream link;
a bypass multiplexer coupled to the transmission port, the reception port, and the core logic, the bypass multiplexer operable to selectively couple the upstream link to the reception port or the local memory; and
breakpoint logic coupled to the bypass multiplexer operable to identify a breakpoint and, responsive to the identification, operable to couple a control signal to the bypass multiplexer to initiate a switch between the reception port and the core logic. - View Dependent Claims (54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64)
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65. A method for controlling communications on an upstream link between a memory module and a memory controller, the method comprising:
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coupling the upstream link to a bypass bus of the memory module, the bypass bus being operable to pass remote data received by the memory hub;
determining a local communication is available from a local memory in the memory module;
identifying a breakpoint in data on the bypass bus; and
coupling the upstream link to the local memory at the breakpoint to allow the upstream link to receive the local communication. - View Dependent Claims (66, 67, 68, 69, 70, 71, 72)
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Specification