Partial page scheme for memory technologies

• US 20060271748A1
• Filed: 05/31/2005
• Published: 11/30/2006
• Est. Priority Date: 05/31/2005
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Jain, Sandeep, Kardach, Jim, Mishra, Animesh
• Granted Patent: US 7,793,037 B2
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

Systems and methods of managing memory provide for detecting a request to activate a memory portion that is limited in size to a partial page size, where the partial page size is less than a full page size associated with the memory. In one embodiment, detecting the request may include identifying a row address and partial page address associated with the request, where the partial page address indicates that the memory portion is to be limited to the partial page size.

Claims

1. A method comprising:

detecting a request to activate a memory portion that is limited in size to a partial page size, the partial page size being less than a full page size associated with the memory.

2. The method of claim 1, further including activating the memory portion based on the request.

3. The method of claim 2, wherein the activating includes isolating at least one sense amplifier of the memory from at least one column of the memory.

4. The method of claim 2, wherein the activating includes using a row decode circuit of the memory to exclude at least one column of the memory from the activating based on the request.

5. The method of claim 1, wherein the detecting includes:

identifying a row address associated with the request; and

identifying a partial page address associated with the request, the partial page address indicating that the memory portion is to be limited to the partial page size.

6. The method of claim 5, wherein identifying the partial page address includes obtaining the partial page address from a mode register of the memory.

7. The method of claim 5, wherein identifying the partial page address includes obtaining the partial page address from a data queue port associated with the memory.

8. The method of claim 5, wherein identifying the partial page address includes obtaining the partial page address from a data mask port associated with the memory.

9. The method of claim 1, wherein the detecting includes detecting a request to activate a dynamic random access memory.

10. The method of claim 1, further including fixing the partial page size during a boot of a system containing the memory.

11. A memory comprising:

page logic to detect a request to activate a portion of the memory that is limited in size to a partial page size, the partial page size to be less than a full page size associated with the memory.

12. The memory of claim 11, wherein the memory is to activate the portion based on the request.

13. The memory of claim 12, further including:

a plurality of columns;

a plurality of sense amplifiers, each sense amplifier corresponding to one of the plurality of columns; and

a plurality of isolation switches, each isolation switch coupled to one of the columns and one of the sense amplifiers, the plurality of isolation switches to isolate at least one of the sense amplifiers from at least one of the columns.

14. The memory of claim 12, further including:

a plurality of rows;

a plurality of columns; and

a row address decoder coupled to the plurality of rows, the row address decoder having row optimization logic to exclude at least one of the plurality of columns from activation based on the request.

15. The memory of claim 11, wherein the page logic is to identify a row address associated with the request and identify a partial page address associated with the request, the partial page address to indicate that the memory portion is to be limited to the partial page size.

16. The memory of claim 15, wherein the memory includes a mode register to store the partial page address, the page logic to retrieve the partial page address from the mode register.

17. The memory of claim 15, wherein the memory includes a data queue port, the page logic to obtain the partial page address from the data queue port.

18. The memory of claim 15, wherein the memory includes a data mask port, the page logic to obtain the partial page address from the data mask port.

19. The memory of claim 11, wherein the memory is a dynamic random access memory.

20. The memory of claim 11, wherein the memory is to fix the partial page size during a boot of a system containing the memory.

21. A system comprising:

a memory having page logic to detect a request to activate a portion of the memory that is limited in size to a partial page size, the partial page size to be less than a full page size associated with the memory;

a processor having a memory controller coupled to the memory to issue the request.

22. The system of claim 21, wherein the memory is to activate the portion based on the request.

23. The system of claim 22, wherein the memory further includes:

a plurality of columns;

a plurality of sense amplifiers, each sense amplifier corresponding to one of the plurality of columns; and

a plurality of isolation switches, each isolation switch coupled to one of the columns and one of the sense amplifiers, the plurality of isolation switches to isolate at least one of the sense amplifiers from at least one of the columns.

24. The system of claim 22, wherein the memory further includes:

a plurality of rows;

a plurality of columns; and

a row address decoder coupled to the plurality of rows, the row address decoder having row optimization logic to exclude at least one of the plurality of columns from activation based on the request.

25. The system of claim 21, wherein the page logic is to identify a row address associated with the request and identify a partial page address associated with the request, the partial page address to indicate that the memory portion is to be limited to the partial page size.

26. The system of claim 25, wherein the memory includes a mode register to store the partial page address, the page logic to retrieve the partial page address from the mode register.

27. The system of claim 25, wherein the memory includes a data queue port, the page logic to obtain the partial page address from the data queue port.

28. The system of claim 25, wherein the memory includes a data mask port, the page logic to obtain the partial page address from the data mask port.

29. The system of claim 21, wherein the memory is a dynamic random access memory.

30. The system of claim 21, wherein the memory is to fix the partial page size during a boot of the system.

31. The system of claim 21, wherein the memory controller is to track the partial page size of the memory portion.