Digital signal processor including a programmable network

• US 20060271765A1
• Filed: 05/24/2005
• Published: 11/30/2006
• Est. Priority Date: 05/24/2005
• Status: Active Grant

• Current Assignee: Coresonic AB (MediaTek, Inc.)
• Original Assignee: Coresonic AB (MediaTek, Inc.)
• Inventors: Tell, Eric Johan, Nilsson, Anders Henrik, Liu, Dake
• Granted Patent: US 7,415,595 B2
• Time in Patent Office: Days
• US Class Current: 712/35
• CPC Class Codes: G06F 15/7857 using interleaved memory addressing G06F12/0607
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30079 Pipeline control instructions, e.g. multicycle NOP
• CPC Class Codes: G06F 9/38 Concurrent instruction execution, e.g. pipeline or look ahead
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3888 controlled by a single instruction for multiple threads [SIMT] in parallel
• CPC Class Codes: G06F 9/3891 organised in groups of units sharing resources, e.g. clusters
• CPC Class Codes: H04B 1/0003 Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain digital baseband systems H04L25/00; digital modulation/demodulation H04L27/00; CDMA H04B1/707; TDMA H04B7/2643; image transmission H04N5/00
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A programmable digital signal processor includes a plurality of memory units, a plurality of accelerator units and a processor core. The digital signal processor also includes a programmable network that may be configured to selectively provide connectivity between the memory units, the accelerator units, and the processor core. Each of the accelerator units may be configured to perform one or more dedicated functions. The processor core may include an execution unit that may be configured to execute instructions that are associated with datapath flow control. The programmable network may be configured to selectively provide the connectivity in response to execution of particular instructions.

Claims

1. A digital signal processor comprising:

a plurality of memory units;

a plurality of accelerator units, each configured to perform one or more dedicated functions;

a processor core including an execution unit configured to execute instructions associated with datapath flow control; and

a programmable network configured to selectively provide connectivity between the plurality of memory units, the plurality of accelerator units, and the processor core in response to execution of the instructions.

2. The processor as recited in claim 1, wherein in response to execution of a particular instruction, the programmable network is configured to couple a given one of the plurality of memory units to a given one of the plurality of accelerator units.

3. The processor as recited in claim 1, wherein in response to execution of a particular instruction, the programmable network is configured to couple one or more memory units of the plurality of memory units to the processor core.

4. The processor as recited in claim 1, wherein in response to execution of a particular instruction, the programmable network is configured to couple together, in a chain, two or more accelerator units of the plurality of accelerator units and to further couple a first accelerator unit of the chain to one of a given one of the plurality of memory units and the processor core.

5. The processor as recited in claim 4, wherein each accelerator unit of the plurality of accelerator units, when connected to another accelerator unit in the chain, is configured to communicate with the accelerator unit to which it is connected without intervention by the processor core.

6. The processor as recited in claim 1, wherein the programmable network includes a plurality of respective interface ports for connection to the processor core, to each of the plurality of memory units, and to each of the plurality of accelerator units.

7. The processor as recited in claim 6, wherein each respective interface port includes a read and write port pair, wherein each of the read and write port pairs includes a read request signal, a data available signal and a plurality of data lines.

8. The processor as recited in claim 1, wherein the processor core further includes a complex execution unit configured to execute complex vector instructions that operate on complex valued data having a real portion and an imaginary portion.

9. The processor as recited in claim 8, wherein the complex execution unit includes a plurality of instruction execution pipelines, each configured to execute a single complex vector instruction per clock cycle.

10. The processor as recited in claim 9, wherein each of the plurality of instruction execution pipelines includes a complex arithmetic logic unit configured to execute the complex vector instructions.

11. The processor as recited in claim 9, wherein the complex execution unit is configured to execute single instruction multiple data (SIMD) instructions.

12. The processor as recited in claim 1, wherein the processor core further includes a complex multiplier accumulator unit configured to perform operations on complex valued data having a real portion and an imaginary portion.

13. The processor as recited in claim 12, wherein the complex multiplier accumulator unit is configured to natively interpret any data as complex valued data.

14. The processor as recited in claim 1, wherein given respective functions of the one or more dedicated functions are associated with different wireless communication standards.

15. The processor as recited in claim 1, wherein each of the plurality of memory units includes an address generation unit configured to generate an address corresponding to a local memory location in response to receiving a read or write transaction.

16. The processor as recited in claim 1, wherein each of the plurality of memory units, the plurality of accelerator units, the processor core, and the programmable network are manufactured on a single integrated circuit.

17. The processor as recited in claim 1, wherein at least some accelerator units of the plurality of accelerator units are configurable hardware implementations of the dedicated functions associated with baseband signal processing.

18. A multimode wireless communication device comprising:

a radio frequency front-end unit configured to transmit and receive radio frequency signals;

a programmable digital signal processor coupled to the radio frequency front-end unit, wherein the programmable digital signal processor includes;

a plurality of memory units;

a plurality of accelerator units, each configured to perform one or more dedicated functions;

a processor core including an execution unit configured to execute instructions associated with datapath flow control;

a programmable network configured to selectively provide connectivity between the plurality of memory units, the plurality of accelerator units, and the processor core in response to execution of the instructions.

19. The wireless communication device as recited in claim 18, wherein in response to execution of a particular instruction, the programmable network is configured to couple a given one of the plurality of memory units to a given one of the plurality of accelerator units.

20. The wireless communication device as recited in claim 18, wherein in response to execution of a particular instruction, the programmable network is configured to couple one or more memory units of the plurality of memory units to the processor core.

21. The wireless communication device as recited in claim 18, wherein in response to execution of a particular instruction, the programmable network is configured to couple together, in a chain, two or more accelerator units of the plurality of accelerator units and to further couple a first accelerator unit of the chain to one of a given one of the plurality of memory units and the processor core.

22. The wireless communication device as recited in claim 21, wherein each accelerator unit of the plurality of accelerator units, when connected to another accelerator unit in the chain, is configured to communicate with the accelerator unit to which it is connected without intervention by the processor core.

23. The wireless communication device as recited in claim 18, wherein the programmable network includes a plurality of respective interface ports for connection to the processor core, to each of the plurality of memory units, and to each of the plurality of accelerator units.

24. The wireless communication device as recited in claim 23, wherein each respective interface port includes a read and write port pair, wherein each of the read and write port pairs includes a read request signal, a data available signal and a plurality of data lines.

25. The wireless communication device as recited in claim 18, wherein the processor core further includes a complex execution unit configured to execute complex vector instructions that operate on complex valued data having a real portion and an imaginary portion.

26. The wireless communication device as recited in claim 25, wherein the complex execution unit includes a plurality of instruction execution pipelines, each configured to execute a single complex vector instruction per clock cycle.

27. The wireless communication device as recited in claim 26, wherein each of the plurality of instruction execution pipelines includes a complex arithmetic logic unit configured to execute the complex vector instructions.

28. The wireless communication device as recited in claim 26, wherein the complex execution unit is configured to execute single instruction multiple data (SIMD) instructions.

29. The wireless communication device as recited in claim 18, wherein the processor core further includes a complex multiplier accumulator unit configured to perform operations on complex valued data having a real portion and an imaginary portion.

30. The wireless communication device as recited in claim 29, wherein the complex multiplier accumulator unit is configured to natively interpret any data as complex valued data.

31. The wireless communication device as recited in claim 18, wherein the programmable digital signal processor is configured to operate within parameters established by a plurality of wireless communication standards.

32. The wireless communication device as recited in claim 18, wherein at least some accelerator units of the plurality of accelerator units are configurable hardware implementations of the dedicated functions associated with baseband signal processing of signals that conform to a plurality of wireless communication standards.