Capacitive microaccelerometers and fabrication methods

• US 20060272414A1
• Filed: 06/01/2006
• Published: 12/07/2006
• Est. Priority Date: 06/03/2005
• Status: Active Grant

• Current Assignee: Georgia Tech Research Corporation (University System of Georgia)
• Original Assignee: Georgia Tech Research Corporation (University System of Georgia)
• Inventors: Abdolvand, Reza, Ayazi, Farrokh, Amini, Babak Vakili
• Granted Patent: US 7,337,671 B2
• Time in Patent Office: Days
• US Class Current: 73/514.320
• CPC Class Codes: B81B 2201/0235 Accelerometers
• CPC Class Codes: B81C 1/00182 Arrangements of deformable or non-deformable structures, e.g. membrane and cavity for use in a transducer
• CPC Class Codes: G01P 15/0802 Details
• CPC Class Codes: G01P 15/125 by capacitive pick-up
• CPC Class Codes: G01P 2015/0814 for translational movement of the mass, e.g. shuttle type
• CPC Class Codes: Y10T 29/49156 with selective destruction of conductive paths

Abstract

Disclosed are moveable microstructures comprising in-plane capacitive microaccelerometers, with submicro-gravity resolution (<200 ng/√Hz) and very high sensitivity (>17 pF/g). The microstructures are fabricated in thick (>100 μm) silicon-on-insulator (SOI) substrates or silicon substrates using a two-mask fully-dry release process that provides large seismic mass (>10 milli-g), reduced capacitive gaps, and reduced in-plane stiffness. Fabricated devices may be interfaced to a high resolution switched-capacitor CMOS IC that eliminates the need for area-consuming reference capacitors. The measured sensitivity is 83 mV/mg (17 pF/g) and the output noise floor is −91 dBm/Hz at 10 Hz (corresponding to an acceleration resolution of 170 ng/√Hz). The IC consumes 6 mW power and measures 0.65 mm² core area.

Claims

1. Sensing apparatus comprising:

a substrate comprising a lower section and an upper section, the upper section comprising a plurality of tethers formed between selected lateral edges and a central region of the upper section, and a plurality of electrodes disposed along selected edges of the upper section;

a seismic mass comprising the central region of the upper section and a portion of the lower section disposed beneath it; and

conductive material disposed along edges of gaps in the upper section defining the seismic mass that reduce respective sizes of the gaps.

2. The apparatus recited in claim 1 wherein the upper section of the substrate comprises a silicon device layer, the portion of the lower section comprises a silicon handle layer, and an insulating layer separates the device layer and handle layer.

3. The apparatus recited in claim 1 wherein two pairs of symmetrically changing capacitances are defined that have a common node at the seismic mass.

4. The apparatus recited in claim 1 wherein the plurality of electrodes comprise parallel plate capacitive electrodes, in which the capacitance changes due to changes in inter-electrode gap spacing.

5. The apparatus recited in claim 1 wherein the plurality of electrodes comprise comb capacitive electrodes, in which the capacitance changes due to change in overlap area of the comb fingers.

6. The apparatus recited in claim 1 wherein an input switching scheme is provided in a switched-capacitor charge amplifier that interfaces with the two pairs of symmetrically changing capacitances.

7. The apparatus recited in claim 6 wherein two pairs of symmetrically changing capacitances comprise capacitance bridge reference capacitors that are integrated into the sense capacitance of the apparatus without compromising sensitivity of the apparatus or increasing its area.

8. The apparatus recited in claim 1 wherein the device layer comprises a plurality of shock stops disposed adjacent edges of the proof mass that prevent adjacent electrodes from contacting each other when the apparatus undergoes acceleration.

9. The apparatus recited in claim 1 wherein the conductive material comprises doped polysilicon.

10. The apparatus recited in claim 2 wherein the plurality of tethers comprise doped polysilicon disposed on portions of the silicon device layer.

11. The apparatus recited in claim 1 wherein selection of the respective masses of the proof mass and tethers allows independent tailoring of the mass and operating frequency of the apparatus.

12. Sensing apparatus comprising:

a silicon-on-insulator substrate comprising a lower silicon handle layer and an upper silicon device layer separated by an insulating layer, which device layer comprises a plurality of tethers formed between selected lateral edges and a central region of the device layer, and a plurality of parallel plate electrodes disposed along selected edges of the device layer;

a seismic mass comprising a central region of the device layer, a portion of the insulating layer disposed beneath the central region of the device layer, and a portion of the handle layer disposed beneath the portion of the insulating layer; and

doped polysilicon disposed along edges of gaps in the device layer defining the seismic mass which reduce respective sizes of the gaps.

13. A method of fabricating a moveable microstructure, comprising:

providing a substrate having upper and lower layers;

etching trenches in the upper layer to define bonding pads, sense electrodes and a proof mass having capacitive gaps formed therebetween, and a plurality of tethers that allow the proof mass to move;

depositing a conformal conductive layer on the substrate to reduce sizes of the capacitive gaps;

etching the conformal conductive layer to remove conformal conductive material at the bottom of the trenches and provide isolation between the bonding pads and the sense electrodes; and

etching the lower layer of the substrate to form extra proof mass that is coupled to the proof mass formed in the upper layer.

14. The method recited in claim 13 wherein the conformal conductive layer is doped to reduce its electrical resistance.

15. The method recited in claim 13 further comprising:

masking and etching the back side of the proof mass to reduce its height.

16. The method recited in claim 13 wherein the substrate comprises a silicon-on-insulator substrate.

17. The method recited in claim 13 wherein the substrate comprises a silicon substrate.

18. A method of fabricating a moveable microstructure, comprising:

providing a low resistivity silicon-on-insulator substrate;

etching trenches on the front side of the substrate to define bonding pads, sense electrodes and a proof mass having capacitive gaps formed therebetween;

depositing a conformal conductive layer on the substrate to reduce capacitive gap sizes;

doping the conformal conductive layer;

etching the conformal conductive layer to remove material at the bottom of the trenches; and

etching the back side of the substrate to provide additional proof mass and to release the microstructure.

19. The method recited in claim 18 further comprising:

growing a thermal silicon oxide layer on both sides of the substrate;

patterning the oxide layer on the both sides of the substrate to form an etch mask;

20. A method of fabricating a moveable microstructure, comprising:

providing a silicon substrate;

etching trenches on the front side of the substrate to define pads, sense electrodes and a proof mass having capacitive gaps formed therebetween;

depositing a conformal conductive layer on the substrate to reduce capacitive gap sizes;

bonding a handle substrate to the top side of the silicon substrate;

etching the back side of the substrate to provide additional proof mass and to release the microstructure by etching the conformal conductive layer to remove material at the bottom of the trenches; and

forming electrical connections through via holes in the handle substrate to the conformal conductive layer adjacent to pads defined in the silicon substrate.

21. The method recited in claim 20 wherein the bonded handle substrate comprises an oxidized silicon substrate.