Differential input circuit with process variation and temperature compensation

• US 20060273171A1
• Filed: 06/01/2005
• Published: 12/07/2006
• Est. Priority Date: 06/01/2005
• Status: Active Grant

• Current Assignee: Zest Labs, Inc.
• Original Assignee: Intelleflex Corporation
• Inventors: Shyu, Jyn-Bang
• Granted Patent: US 7,611,066 B2
• Time in Patent Office: Days
• US Class Current: 235/435
• CPC Class Codes: H03D 1/10 of diodes

Abstract

Systems with semiconductor devices that are DC-biased at either their weak inversion (i.e., sub-threshold) region or their strong inversion region. In a preferred embodiment using semiconductor devices (e.g., NMOS, PMOS, etc.), a gate to source voltage (Vgs) is slightly below the threshold voltage (Vtn) of the device. These weakly turned-on semiconductor devices increase the receiving AC sensitivity of an AM-Detector compared to that of a conventional AM-Detector without any DC-biasing. Further, the compensating bias voltage (Vbias) compensates for one or both of the ambient temperature change and the foundry'"'"'s process variation of the various semiconductor devices.

Claims

1. A differential input circuit, comprising:

a first set of semiconductor devices coupled to a first alternating current (AC) signal input;

a second set of semiconductor devices coupled to a second AC signal input; and

a biasing circuit providing a direct current (DC) bias voltage to gates of the semiconductor devices.

2. A circuit as recited in claim 1, wherein the semiconductor devices are selected from a group consisting of NMOS, PMOS, MOSFET, MESFET, BJT, and JFET devices.

3. A circuit as recited in claim 1, wherein the first and second sets of semiconductor devices form at least part of a differential input full wave bridging rectifier radio frequency (RF) amplitude modulation (AM) detector.

4. A circuit as recited in claim 3, wherein the semiconductor devices in each set are cross connected.

5. A circuit as recited in claim 1, wherein the biasing circuit includes a semiconductor device that has substantially the same temperature response as the semiconductor devices in the sets of semiconductor devices.

6. A circuit as recited in claim 1, wherein the biasing circuit includes a semiconductor device that has substantially the same construction as the semiconductor devices in the sets of semiconductor devices.

7. A circuit as recited in claim 1, wherein the biasing voltage biases the semiconductor devices at their inversion region.

8. A circuit as recited in claim 1, wherein each of the semiconductor devices has a switching threshold, wherein the bias voltage urges each of the semiconductor device towards a sub-threshold region thereof.

9. A circuit as recited in claim 1, wherein the biasing circuit includes a current mirror.

10. A circuit as recited in claim 1, further comprising at least one resistor for isolating the biasing circuit from the AC signal inputs.

11. A circuit as recited in claim 1, further comprising a capacitor coupled to each of the AC signal inputs for isolating the AC signal inputs from the biasing circuit.

12. A circuit as recited in claim 1, wherein the semiconductor devices have a threshold voltage of at least about 250 millivolts.

13. A circuit as recited in claim 1, wherein a sensitivity of the circuit decreases as signal levels from the AC signal inputs increase above a threshold voltage of the semiconductor devices.

14. A Radio Frequency Identification (RFID) system, comprising:

a plurality of RFID tags each having the circuit of claim 1;

and

an RFID interrogator in communication with the RFID tags.

15. A differential input radio frequency amplitude modulation detector circuit, comprising:

a first set of semiconductor devices coupled to a first alternating current (AC) signal input;

a second set of semiconductor devices coupled to a second AC signal input;

an output coupled to the sets of semiconductor devices; and

a biasing circuit providing a direct current (DC) bias voltage to the semiconductor devices,

wherein the semiconductor devices function substantially as zero voltage bias threshold device under the influence of the bias voltage.

16. A circuit as recited in claim 15, wherein the semiconductor devices are selected from a group consisting of NMOS, PMOS, MOSFET, MESFET, BJT, and JFET devices.

17. A circuit as recited in claim 15, wherein the circuit is a differential input full wave bridging rectifier radio frequency (RF) amplitude modulation (AM) detector.

18. A circuit as recited in claim 15, wherein the circuit is a cross-connected full wave bridging rectifier radio frequency (RF) amplitude modulation (AM) detector.

19. A circuit as recited in claim 15, wherein the biasing circuit includes a semiconductor device that has substantially the same temperature response as the semiconductor devices in the sets of semiconductor devices.

20. A circuit as recited in claim 15, wherein the biasing circuit includes a semiconductor device that has substantially the same construction as the semiconductor devices in the sets of semiconductor devices.

21. A circuit as recited in claim 15, wherein the biasing voltage biases the semiconductor devices at their inversion region.

22. A circuit as recited in claim 15, wherein each of the semiconductor devices has a switching threshold, wherein the bias voltage urges each of the semiconductor devices towards a sub-threshold region thereof.

23. A circuit as recited in claim 15, wherein each of the semiconductor devices has a threshold voltage, wherein the bias voltage is less than about 100 mV below the threshold voltage.

24. A circuit as recited in claim 15, wherein the biasing circuit includes a current mirror.

25. A circuit as recited in claim 15, further comprising at least one resistor for isolating the biasing circuit from the AC signal inputs.

26. A circuit as recited in claim 15, further comprising a capacitor coupled to each of the AC signal inputs for isolating the AC signal inputs from the biasing circuit.

27. A circuit as recited in claim 15, wherein the semiconductor devices have a threshold voltage of at least about 250 millivolts.

28. A circuit as recited in claim 15, wherein a sensitivity of the circuit decreases as signal levels from the AC signal inputs increase above a threshold voltage of the semiconductor devices.

29. A Radio Frequency Identification (RFID) system, comprising:

a plurality of RFID tags each having the circuit of claim 15;

and

an RFID interrogator in communication with the RFID tags.

30. A full wave rectifier circuit having an alternating current (AC) section and a direct current (DC) section.

31. A Radio Frequency Identification (RFID) system, comprising:

a plurality of RFID tags each having the circuit of claim 30;

and

an RFID interrogator in communication with the RFID tags.

32. A circuit wherein a sensitivity of the circuit decreases as levels of incoming alternating current (AC) signals increase above a threshold voltage of semiconductor devices of the circuit.

33. A Radio Frequency Identification (RFID) system, comprising:

a plurality of RFID tags each having the circuit of claim 32;

and

an RFID interrogator in communication with the RFID tags.

34. A circuit, comprising:

a set of semiconductor devices coupled to an alternating current (AC) signal input;

a biasing circuit providing a direct current (DC) bias voltage to gates of the semiconductor devices,

wherein the biasing circuit includes a first device having substantially the same construction as the semiconductor devices, the first device regulating the bias voltage at a level sufficient to bias the semiconductor devices at inversion regions thereof.

35. A circuit as recited in claim 34, wherein the biasing circuit compensates for variations in fabrication parameters of the semiconductor devices, wherein the biasing circuit also compensates for temperature variations affecting the semiconductor devices.

36. A Radio Frequency Identification (RFID) system, comprising:

a plurality of RFID tags each having the circuit of claim 34;

and

an RFID interrogator in communication with the RFID tags.