Ic tag

• US 20060273179A1
• Filed: 05/14/2003
• Published: 12/07/2006
• Est. Priority Date: 05/15/2002
• Status: Active Grant

• Current Assignee: Lintec Corporation
• Original Assignee: Lintec Corporation
• Inventors: Taguchi, Katsuhisa, Hasegawa, Tomoyuki, Yamakage, Masateru, Takahara, Toru
• Granted Patent: US 7,540,427 B2
• Time in Patent Office: Days
• US Class Current: 235/492
• CPC Class Codes: G06K 19/0739 the incapacitated circuit being part of an antenna
• CPC Class Codes: G06K 19/07749 the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card

Abstract

The present invention provides an IC tag which has a structure comprising a first adhesive layer formed on a surface of a substrate sheet, an electronic circuit and an IC chip connecting both ends of the electronic circuit, both formed on the surface of the first adhesive layer, and a second adhesive layer covering the electronic circuit and the IC chip. The IC tag further includes a release agent layer formed at positions corresponding to the both ends of the electronic circuit and located at the interface between the substrate sheet and the first adhesive layer. When the IC tag attached to an article is peeled off, the built-in electronic circuit is surely broken.

Claims

1. An IC tag which has a structure comprising a first adhesive layer laminated on a surface of a substrate sheet, an electronic circuit and an IC chip connecting both ends of the electronic circuit, both the electronic circuit and the IC chip being formed on a surface of the first adhesive layer, and a second adhesive layer laminated for covering the electronic circuit and the IC chip, wherein a release agent layer is further formed at positions corresponding to both ends of the electronic circuit and located at the interface between the substrate sheet and the first adhesive layer.

2. The IC tag as claimed in claim 1, wherein the release agent layer if formed to cover the range of 20 to 90 percents of an area surrounded by an outside circumference of the electronic circuit throughout the first adhesive layer.

3. The IC tag as claimed in claim 1, wherein a release liner is formed on a surface of the second adhesive layer.