Trenched MOSFET device with contact trenches filled with tungsten plugs

• US 20060273385A1
• Filed: 02/28/2006
• Published: 12/07/2006
• Est. Priority Date: 06/06/2005
• Status: Abandoned Application

• Current Assignee: M-Mos Semiconductor Sdn. Bhd.
• Original Assignee: M-Mos Semiconductor Sdn. Bhd.
• Inventors: Hshieh, Fwu-Iuan
• Application Number:
  US11/363,824
• Publication Number:
  US 20060273385A1
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/48624 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48655 Nickel (Ni) as principal constituent
• CPC Class Codes: H01L 2224/48724 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48755 Nickel (Ni) as principal constituent
• CPC Class Codes: H01L 2224/4903 Connectors having different sizes, e.g. different diameters
• CPC Class Codes: H01L 2224/49051 Connectors having different shapes
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/73221 Strap and wire connectors
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 24/26 Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/40 of an individual strap connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 29/0615 : by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/402 : Field plates
• CPC Class Codes: H01L 29/41766 : with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4238 : characterised by the surface lay-out
• CPC Class Codes: H01L 29/456 : on silicon
• CPC Class Codes: H01L 29/66727 : with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 : with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01007 : Nitrogen [N]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/0133 : Ternary Alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/20755 : larger or equal to 50 microns less than 60 microns
• CPC Class Codes: H01L 2924/2076 : equal to or larger than 100 microns
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A trenched semiconductor power device that includes a trenched gate disposed in an extended continuous trench surrounding a plurality of transistor cells in an active cell area and extending as trench-gate fingers to intersect with a trenched gate under the gate metal runner at a termination area. At least one of the trench-gate fingers intersects with the trenched gate under the gate metal runner near the termination area having trench intersection regions vulnerable to have a polysilicon void developed therein. At least a gate contact trench opened through an insulation layer covering the semiconductor power device wherein the gate contact trench penetrating from the insulation layer and extending into the gate polysilicon and the gate contact trench is opened in an area away from the trench intersection regions.

Claims

1. A trenched semiconductor power device comprising a trenched gate disposed in an extended continuous trench surrounding a plurality of transistor cells in an active cell area and extending as trench-gate fingers to intersect with a trenched gate underneath gate runner metal near a termination area, wherein:

at least one of said trench-gate fingers intersect with said trenched gate underneath gate runner metal in said termination area having trench intersection regions vulnerable to have a polysilicon void developed therein; and

at least a gate contact trench opened through an insulation layer covering said semiconductor power device wherein said gate contact trench penetrating from said insulation layer and extending into a trench-filling material in said trenched gate underneath gate runner metal and said gate contact trench is opened in an area away from said trench intersection regions.

2. The trenched semiconductor power device of claim 1 wherein:

said trench intersection regions constituting a T-shaped intersection region.

3. The trenched semiconductor power device of claim 1 wherein:

said gate contact trench is filled with a conductive gate contact plug.

4. The trenched semiconductor power device of claim 1 wherein:

said gate contact trench is filled with a tungsten gate contact plug.

5. The trenched semiconductor power device of claim 1 wherein:

said gate contact trench is filled with a tungsten gate contact plug surrounded with a Ti/TiN barrier layer.

6. The trenched semiconductor power device of claim 1 wherein:

said trenched gate underneath gate runner metal is configured as an open stripe extending from and intersecting to said trench-gate fingers as an L-shaped trenched gate underneath gate runner metal with said gate contact trench opened at a distance S away from an near edge of each of said trench-gate fingers where S is greater than half of a width of said trench-gate fingers.

7. The trenched semiconductor power device of claim 1 wherein:

said trenched gate underneath gate runner metal is configured as an open stripe extending from and intersecting to said trench-gate fingers as an expanded square-shaped trenched gate underneath gate runner metal with said gate contact trench opened at a distance S away from an intersecting edge of each of said trench-gate fingers with said expanded square shaped trenched gate underneath gate runner metal where S is greater than a width of said trench-gate fingers.

8. The trenched semiconductor power device of claim 1 wherein:

said trenched gate underneath gate runner metal is configured as a no-open-end trenched gate underneath gate runner metal perpendicularly intersecting to said trench-gate fingers with said gate contact trench opened at a distance S away from an intersecting edge of each of said trench-gate fingers with said no-open-end trenched gate underneath gate runner metal where S is greater than half of a width of said trench-gate fingers.

9. The trenched semiconductor power device of claim 1 wherein:

said trenched gate underneath gate runner metal is configured as an open stripe extending from and intersecting to said trench-gate fingers as an expanded rectangular-shaped trenched gate underneath gate runner metal with said gate contact trench opened at a distance S away from an intersecting edge of each of said trench-gate fingers with said expanded rectangular shaped trenched gate underneath gate runner metal where S is greater than a width of said trench-gate fingers.

10. The trenched semiconductor power device of claim 1 wherein:

said trenched gate underneath gate runner metal is configured as an open stripe extending from and having a greater width than said trench-gate fingers wherein said open stripe allowing a body-dopant region disposed adjacent to a source region of said semiconductor power device connecting to another body dopant region underneath a gate runner metal whereby said gate runner metal can function as a field plate.

11. The trenched semiconductor power device of claim 1 wherein:

said trenched gate underneath gate runner metal is configured as an open stripe extending from and intersecting to said trench-gate fingers as an L-shaped trenched gate underneath gate runner metal having a greater width than said trench-gate fingers wherein said L-shaped open trenched gate underneath gate runner metal allowing a body region disposed adjacent to a source region of said semiconductor power device connecting to another body dopant region underneath a gate runner metal whereby said gate runner metal can function as a field plate

12. The trenched semiconductor power device of claim 1 further comprising:

a metal layer formed on top of said insulation layer and patterned into a gate metal and a source metal with a TiN/dielectric layer formed on top of said metal layer for providing a pattern recognition mark for wire bonding

13. The trenched semiconductor power device of claim 1 further comprising:

a metal layer formed on top of said insulation layer and patterned into a gate metal and a source metal with at least a pattern-recognition hole formed on predefined location of said metal layer for providing a pattern recognition mark for wire bonding

14. The trenched semiconductor power device of claim 1 further comprising:

a metal layer formed on top of said insulation layer and patterned into a gate metal and a source metal with a pattern-recognition hole formed on a intersection corner between said gate metal and source metal of said metal layer for providing a pattern recognition mark for wire bonding.

15. The trenched semiconductor power device of claim 1 further comprising:

a metal layer formed on top of said insulation layer and patterned into a gate metal and a source metal with a first pattern-recognition hole formed on a intersection corner between said gate metal and source metal and a second pattern recognition hole on a source metal corner diagonally opposite said first pattern-recognition hole in said metal layer for providing a pattern recognition mark for wire bonding.

16. The trenched semiconductor power device of claim 1 wherein:

said gate contact trench penetrating from said insulation layer and extending into a trench-filling material of doped polysilicon in said trenched gate underneath gate runner metal.

17. A trenched semiconductor power device comprising a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate, wherein said semiconductor power device further comprising:

at least two contact trenches opened through an insulation layer covering said semiconductor device wherein said contact trenches extending into a trench-filling material of said trenched gate and said body region and filled with a gate contact plug and a source contact plug for electrically contact respectively to a gate metal and a source metal disposed on top of said insulation layer wherein said gate metal and source metal further include a pattern recognition mark for wire bonding.

18. The trenched semiconductor power device of claim 17 further comprising:

said pattern recognition mark further comprising a TiN/dielectric layer formed on said source metal and gate metal for providing a pattern recognition mark for wire bonding.

19. The trenched semiconductor power device of claim 17 further comprising:

said pattern recognition mark further comprising at least a pattern-recognition hole formed on predefined location of said gate metal or said source metal for providing a pattern recognition mark for wire bonding

20. The trenched semiconductor power device of claim 17 further comprising:

said pattern recognition mark further comprising a pattern-recognition hole formed on a intersection corner between said gate metal and source metal of said metal layer for providing a pattern recognition mark for wire bonding.

21. The trenched semiconductor power device of claim 17 further comprising:

said pattern recognition mark further comprising a first pattern-recognition hole formed on a intersection corner between said gate metal and source metal and a second pattern recognition hole on a source metal corner diagonally opposite said first pattern-recognition hole in said metal layer for providing a pattern recognition mark for wire bonding.

22. The trenched semiconductor power device of claim 17 wherein:

said at least two contact trenches are filled with at least two conductive contact plugs for electrically contacting said source region and said trenched gate.

23. The trenched semiconductor power device of claim 17 wherein:

said at least two contact trenches are filled with at least two tungsten contact plugs for electrically contacting said source region and said trenched gate.

24. The trenched semiconductor power device of claim 17 wherein:

said at least two contact trenches are filled with at least two tungsten contact plugs surrounded with a Ti/TiN barrier layer for electrically contacting said source region and said trenched gate.

25. The trenched semiconductor power device of claim 17 further comprising:

said pattern recognition mark further comprising a TiN/oxide layer formed on said source metal and gate metal for providing a pattern recognition mark for wire bonding.

26. The trenched semiconductor power device of claim 17 further comprising:

said pattern recognition mark further comprising a TiN/SiON layer formed on said source metal and gate metal for providing a pattern recognition mark for wire bonding.

27. The trenched semiconductor power device of claim 17 further comprising:

said pattern recognition mark further comprising a TiN/nitride layer formed on said source metal and gate metal for providing a pattern recognition mark for wire bonding.

28. The trenched semiconductor power device of claim 17 further comprising:

said pattern recognition mark further comprising a TiN/Combination of oxide, nitride and SiON layer of a different color formed on said source metal and gate metal for providing a pattern recognition mark for wire bonding.

29. A method for fabricating a trenched semiconductor power device comprising steps of forming a trenched gate as an extended continuous trench surrounding a plurality of transistor cells in an active cell area and extending as trench-gate fingers to intersect with a trenched gate underneath gate runner metal near a termination area having a trench intersection region and forming each of said transistor cells surrounded by said trenched gate with a body region encompassing a source region therein with a drain region formed on a bottom surface of a substrate, said method further comprising:

forming an overlying insulation layer and opening at least a gate contact trench penetrating through said insulation layer and extending into a trench-filling material in said trenched gate under gate runner metal by opening said gate contact trench in an area away from said trench intersection region to prevent a vulnerability to a polysilicon void developed in said trench intersection region.

30. The method of claim 29 further comprising:

opening at least a source contact trench through said insulation layer for contacting said source region in at least one of said transistor cells and filling said gate contact trench and source contact trench with a gate contact plug and a source contact plug; and

forming a metal layer on top of said insulation layer and patterning said metal layer into a gate metal and a source metal to electrically contact respectively to said gate contact plug and said source contact plug and forming said gate metal and source metal with a pattern recognition mark for wire bonding.

31. The trenched semiconductor power device of claim 30 wherein:

said step of filling said gate contact trench and source contact trench comprising step of filling said gate contact trench with a tungsten gate contact plug and a tungsten source contact plug.