Trench-gate field effect transistors and methods of forming the same

• US 20060273386A1
• Filed: 05/24/2006
• Published: 12/07/2006
• Est. Priority Date: 05/26/2005
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Probst, Dean E., Yilmaz, Hamza, Kocon, Christopher Boguslaw, Calafut, Daniel, Yedinak, Joseph A., Marchant, Bruce D., Dolny, Gary M., Sapp, Steven P., Kraft, Nathan L., Grebs, Thomas E., Ridley, Rodney S.
• Granted Patent: US 7,504,303 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A field effect transistor includes a body region of a first conductivity type over a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminates within the semiconductor region. At least one conductive shield electrode is disposed in the gate trench. A gate electrode is disposed in the gate trench over but insulated from the at least one conductive shield electrode. A shield dielectric layer insulates the at lease one conductive shield electrode from the semiconductor region. A gate dielectric layer insulates the gate electrode from the body region. The shield dielectric layer is formed such that it flares out and extends directly under the body region.

Claims

1-17. -17. (canceled)

18. A method of forming a shielded gate field effect transistor, comprising:

forming a hard mask over a silicon region, the hard mask comprising a protective layer;

patterning the hard mask to define openings therein;

etching the silicon region through the openings in the hard mask to thereby form trenches extending into the silicon region;

forming a shield dielectric layer lining sidewalls and bottom of each trench;

forming a shield electrode in a bottom portion of each trench, the shield electrode being insulated from the silicon region by the shield dielectric layer;

forming protective spacers along upper sidewalls of each trench;

forming an inter-electrode dielectric over the shield electrode in each trench, the protective spacers and the protective layer of the hard mask preventing formation of inter-electrode dielectric along upper sidewalls of each trench and over mesa surfaces adjacent each trench; and

forming a gate electrode in each trench over the inter-electrode dielectric.

19. The method of claim 18 wherein the protective layer in the hard mask comprises nitride.

20. The method of claim 18 wherein the hard mask comprises oxide-nitride-oxide composite layer.

21. The method of claim 18 wherein the protective spacers comprise nitride.

22. The method of claim 18 wherein the step of forming an inter-electrode dielectric comprises performing thermal oxidation.

23. The method of claim 18 wherein the step of forming protective spacers comprises:

forming a nitride layer lining the upper sidewalls of each trench and extending over mesa regions between the trenches; and

anisotropically etching the nitride layer to thereby remove horizontally extending portions of the nitride layer.

24. The method of claim 18 further comprising:

prior to forming the gate electrode;

removing the protective spacers; and

lining upper sidewalls of each trench with a gate dielectric layer.

25. The method of claim 18 further comprising:

forming a body region in the silicon region, the body region and silicon region being of opposite conductivity type; and

forming source regions in the body region, the source regions and the body region being of opposite conductivity type.

26. The method of claim 25 wherein the body region is formed prior to forming the trenches.

27. The method of claim 18 further comprising:

forming a body region in the silicon region, the body region and silicon region being of opposite conductivity type;

forming a dielectric cap over each gate electrode such that the dielectric caps over every two adjacent trenches define an exposed surface of the body region therebetween;

recessing the exposed surface of the body region between every two adjacent dielectric caps; and

performing heavy body implant to form a heavy body region along each recessed surface of the body region, the heavy body regions and the silicon region being of opposite conductivity type.

28. The method of claim 18 further comprising:

forming a body region in the silicon region, the body region and silicon region being of opposite conductivity type;

performing a source implant to form a highly doped region extending in the body region between every two adjacent trenches, the highly doped region and the body region being of opposite conductivity type;

forming a dielectric cap over each gate electrode such that the dielectric caps over every two adjacent trenches define an exposed surface of the highly doped region therebetween;

recessing the exposed surface of the highly doped region between every two adjacent dielectric caps to a depth below a depth of the highly doped region such that remaining portions of each highly doped region form source regions; and

performing heavy body implant to form a heavy body region along each recessed surface of the body region, the heavy body regions and the silicon region being of opposite conductivity type.

29. The method of claim 18 wherein the shield electrode and gate electrode comprise polysilicon, and the shield dielectric layer and the gate dielectric layer comprise oxide.

30. A method of forming a shielded gate field effect transistor, comprising:

forming a hard mask over a silicon region, the hard mask comprising an oxide- nitride-oxide composite layer;

patterning the hard mask to define openings therein;

etching the silicon region through the openings in the hard mask to thereby form trenches extending into the silicon region;

forming a shield dielectric layer lining sidewalls and bottom of each trench;

forming a shield electrode in a bottom portion of each trench, the shield electrode being insulated from the silicon region by the shield dielectric layer;

forming nitride spacers along upper sidewalls of each trench;

performing thermal oxidation to form a layer of thermal oxide over the shield electrode in each trench, the nitride spacers and the hard mask preventing formation of thermal oxide along upper sidewalls of each trench and over mesa surfaces adjacent each trench; and

forming a gate electrode in each trench over the inter-electrode dielectric.

31. The method of claim 30 wherein the step of forming nitride spacers comprises:

forming a nitride layer lining the upper sidewalls of each trench and extending over the mesa regions; and

anisotropically etching the nitride layer to thereby remove horizontally extending portions of the nitride layer.

32. The method of claim 30 further comprising:

prior to forming the gate electrode;

removing the nitride spacers; and

lining upper sidewalls of each trench with a gate dielectric layer.

33. The method of claim 30 further comprising:

forming a body region in the silicon region, the body region and silicon region being of opposite conductivity type; and

forming source regions in the body region, the source regions and the body region being of opposite conductivity type.

34. The method of claim 33 wherein the body region is formed prior to forming the trenches.

35. The method of claim 30 further comprising:

forming a body region in the silicon region, the body region and silicon region being of opposite conductivity type;

forming a dielectric cap over each gate electrode such that the dielectric caps over every two adjacent trenches define an exposed surface of the body region therebetween;

recessing the exposed surface of the body region between every two adjacent dielectric caps; and

performing heavy body implant to form a heavy body region along each recessed surface of the body region, the heavy body regions and the silicon region being of opposite conductivity type.

36. The method of claim 30 further comprising:

forming a body region in the silicon region, the body region and silicon region being of opposite conductivity type;

performing a source implant to form a highly doped region extending in the body region between every two adjacent trenches, the highly doped region and the body region being of opposite conductivity type;

forming a dielectric cap over each gate electrode such that the dielectric caps over every two adjacent trenches define an exposed surface of the highly doped region therebetween;

recessing the exposed surface of the highly doped region between every two adjacent dielectric caps to a depth below a depth of the highly doped region such that remaining portions of each highly doped region form source regions; and

performing heavy body implant to form a heavy body region along each recessed surface of the body region, the heavy body regions and the silicon region being of opposite conductivity type.

37. The method of claim 30 wherein the shield electrode and gate electrode comprise polysilicon, and the shield dielectric layer and the gate dielectric layer comprise oxide.

38. The method of claim 30 wherein the silicon region comprises a substrate and an epitaxial layer over the substrate, the epitaxial layer and the substrate being of the same conductivity type, the epitaxial layer having a lower doping concentration than the substrate, the method further comprising:

forming a body region in the epitaxial layer, the body region and the epitaxial layer being of opposite conductivity type; and

forming source regions in the body region, the source regions and the body region being of opposite conductivity type.