CMOS devices for low power integrated circuits

• US 20060273391A1
• Filed: 06/01/2005
• Published: 12/07/2006
• Est. Priority Date: 06/01/2005
• Status: Abandoned Application

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Mi-Chang, Diaz, Carlos H.
• Application Number:
  US11/142,214
• Publication Number:
  US 20060273391A1
• Time in Patent Office: Days
• US Class Current: 257/335
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/28247 passivation or protection of the electrode, e.g. using re-oxidation
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A preferred embodiment of the invention provides a semiconductor fabrication method. An embodiment comprises forming a MOS device and thermally oxidizing the MOS device to form a gate dielectric substantially thicker at a gate dielectric edge than that at a gate dielectric center. Embodiments further comprise performing a source/drain ion implant to form an asymmetric source/drain, wherein the source region includes a high leakage source junction, and wherein the drain region includes a low leakage drain junction. Other embodiments of the invention comprise a MOS device formed in a semiconductor substrate, wherein the device has improved resistance to floating body effects. Still other embodiments include a CMOS device for low power integrated circuits.

Claims

1. A low-standby power device comprising:

a substrate;

an active device in the substrate, wherein the active device comprises a source, a drain, and a gate;

an asymmetric halo region in the substrate; and

a gate dielectric over the substrate, wherein a gate dielectric thickness at a gate edge is substantially thicker than the gate dielectric thickness at a gate center.

2. The device of claim 1, wherein the device comprises a non-DRAM cell device.

3. The device of claim 1, wherein the substrate comprises silicon.

4. The device of claim 1, wherein the substrate comprises germanium.

5. The device of claim 1, wherein the substrate comprises silicon germanium.

6. The device of claim 1, wherein the substrate comprises silicon on insulator (SOI).

7. The device of claim 1, wherein the asymmetric halo region comprises a low leakage drain junction substantially without pocket or halo implants.

8. The device of claim 1, wherein the asymmetric halo region comprises a low leakage drain junction comprising a graded drain junction.

9. The device of claim 8, wherein the low leakage drain junction comprises an implant concentration less than 1E18 cm-3 under a drain extension side.

10. The device of claim 1, wherein the asymmetric halo region comprises a high leakage source junction with pocket or halo implants.

11. The device of claim 10, wherein the high leakage source junction comprises a pocket implant region with a concentration between 1E18 and 1E19 cm-3 under a source extension side.

12. The device of claim 10, wherein the high leakage source junction comprises a halo implant region with a concentration between 1E18 and 1E19 cm-3 under a source extension side.

13. The device of claim 1, wherein the asymmetric halo region comprises a different extension depth in the source and in the drain.

14. The device of claim 1, wherein the gate edge thickness is greater than 20% thicker than the gate center thickness.

15. A low-standby power circuit comprising:

a current flow controlling device between a power/ground supply and a logic/analog circuit, wherein the current flow controlling device comprises an asymmetric halo region in a substrate.

16. The circuit of claim 15, wherein the current flow controlling device comprises a gate dielectric over the substrate, where a gate dielectric thickness at a gate edge is substantially thicker than the gate dielectric thickness at a gate center.

17. The circuit of claim 15, further comprising gate arrays with restricted gate orientation placement.

18. The circuit of claim 15, further comprising standard-cells with restricted gate orientation placement.

19. The circuit of claim 15, further comprising a plurality of the current flow controlling devices;

wherein the plurality of current flow controlling devices controls the power supply that is electrically connected to gate arrays or standard cell logic circuits.

20. The circuit of claim 15, further comprising a plurality of the current flow controlling devices;

wherein the plurality of current flow controlling devices controls the ground supply that is electrically connected to gate arrays or standard cell logic circuits.

21. The circuit of claim 15, further comprising a plurality of the current flow controlling devices;

wherein the plurality of current flow controlling devices have a same longitudinal gate orientation within a die or an integrated circuit.