Multiple spacer steps for pitch multiplication

• US 20060273456A1
• Filed: 06/02/2005
• Published: 12/07/2006
• Est. Priority Date: 06/02/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Sandhu, Gurtej, Rueger, Neal R., Sant, Sanket
• Granted Patent: US 7,560,390 B2
• Time in Patent Office: Days
• US Class Current: 257/734
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/3085 characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/3088 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers formed around a plurality of mandrels is removed and alternating layers, formed of two mutually selectively etchable materials, are deposited around the remaining spacers. Layers formed of one of the materials are then etched, leaving behind vertically-extending layers formed of the other of the materials, which form a mask pattern. Alternatively, instead of depositing alternating layers, amorphous carbon is deposited around the remaining spacers followed by a plurality of cycles of forming pairs of spacers on the amorphous carbon, removing one of the pairs of spacers and depositing an amorphous carbon layer. The cycles can be repeated to form the desired pattern. Because the critical dimensions of some features in the pattern can be set by controlling the width of the spaces between spacers, exceptionally small mask features can be formed.

Claims

1. A process for semiconductor processing, comprising:

providing a plurality of mandrels on a level above a substrate;

forming spacers on sidewalls of the mandrels;

removing the mandrels and some of the spacers; and

processing the substrate through a mask pattern comprising features defined by a remainder of the spacers.

2. The process of claim 1, further comprising forming a pattern on at least one other level above the spacers.

3. The process of claim 2, further comprising consolidating the pattern on the level of the spacers.

4. The process of claim 3, further comprising consolidating the pattern and an other pattern defined by the spacers in a layer underneath the level of the spacers to form the mask pattern.

5. The process of claim 2, wherein the pattern on at least one other level comprises pitch multiplied spacers.

6. The process of claim 2, wherein the at least one other level are two levels.

7. The process of claim 1, wherein the spacers occupy a first level and further comprising transferring a pattern defined by the remainder of the spacers into a layer underlying the first level.

8. The process of claim 7, further comprising forming an other pattern of spacers on the first level and transferring the other pattern into the layer underlying the first level.

9. The process of claim 1, further comprising:

sequentially conformally depositing a plurality of layers over the remainder of the spacers, each layer following a contour of the remainder of the spacers; and

selectively anisotropically etching some of the layers to leave a plurality of features and the remainder of the spacers separated by spaces, wherein the mask pattern comprises the features and the remainder of the spacers.

10. The process of claim 9, wherein sequentially conformally depositing comprises alternatingly depositing layers, each layer formed of one of two materials.

11. The process of claim 9, wherein selectively anisotropically etching comprises performing a chemical mechanical polishing process on the layers and the spacers.

12. The process of claim 1, wherein the mandrels are formed of amorphous carbon and the spacers are formed of silicon oxide.

13. The process of claim 12, wherein providing the plurality of mandrels comprises:

defining a pattern in photoresist;

and

transferring the pattern to an amorphous carbon layer to form the plurality of mandrels.

14. The process of claim 13, wherein forming spacers on sidewalls of the mandrels comprises:

blanket depositing a layer of silicon oxide over the mandrels; and

etching the silicon oxide from horizontal surfaces.

15. The process of claim 1, wherein removing the mandrels and some of the spacers comprises etching away every other spacer.

16. The process of claim 1, wherein removing the mandrels and some of the spacers comprises:

depositing a protective layer around the mandrels and the spacers;

patterning the protective layer to expose the some of the spacers; and

etching the exposed spacers.

17. The process of claim 16, wherein removing the mandrels and the some of the spacers comprises simultaneously removing the protective layer and the mandrels.

18. The process of claim 1, wherein processing the substrate comprises etching the substrate to transfer the mask pattern into the substrate.

19. The process of claim 18, wherein etching the substrate defines conductive interconnect lines in the substrate.

20. The process of claim 1, further comprising transferring the mask pattern to one or more layers between the substrate and the level of the remainder of the spacers before processing the substrate.

21. The process of claim 20, wherein the one or more layers comprises an amorphous carbon layer disposed on the substrate and a silicon oxide layer disposed on the amorphous carbon layer.

22-49. -49. (canceled)

50. A method for processing semiconductor substrates, comprising:

forming a plurality of spacers by pitch multiplication on a level over a semiconductor substrate; and

forming a mask pattern on a mask layer directly underlying the spacers by etching through a pattern defined by the plurality of spacers, wherein the mask pattern comprises one or more mask features disposed between and separated from positions of immediately adjacent spacers.

51. The method of claim 50, wherein a distance directly between features in the mask pattern is less than a resolution limit of a photolithographic method used in forming the plurality of spacers by pitch multiplication.

52. The method of claim 51, wherein the distance directly between features in the mask pattern is about 25 nm or less.

53. The method of claim 52, wherein each spacer is separated from its closest adjacent spacer by about 175 nm.

54. The method of claim 50, wherein forming the mask pattern comprises:

removing some of the plurality of spacers to form a first plurality of single spacers;

forming a second plurality of single spacers on a level over the first plurality of single spacers;

forming a third plurality of single spacers on a level over the second plurality of single spacers; and

consolidating each of the patterns formed by the first, the second and the third plurality of single spacers on the mask layer by etching through each of the patterns formed by the first, the second and the third plurality of single spacers.

55. The method of claim 50, wherein forming the mask pattern comprises:

removing some of the plurality of spacers to form a plurality of single spacers;

depositing a plurality of layers having an alternating composition on the plurality of single spacers, wherein depositing comprises performing an atomic layer deposition;

planarizing the spacers and the plurality of layers; and

selectively etching some of the layers to define the mask pattern.

56-66. -66. (canceled)

67. A method of semiconductor processing, comprising:

providing a first set of mask features;

forming a plurality of spacers over features of the first set of mask features;

consolidating the first set of mask features and the plurality of spacers on the same level to form a mask pattern, wherein the plurality of spacers define features in the mask pattern between features defined by the first set of mask features; and

processing a substrate through the mask pattern.

68. The method of claim 67, wherein the first set of mask features comprises spacers.

69. The method of claim 67, further comprising forming an other plurality of spacers over the plurality of spacers, wherein consolidating the first set of mask features and the plurality of spacers on the same level to comprises consolidating the first set of mask features, the plurality of spacers and the other plurality of spacers on the same level to form a mask pattern.

70. The method of claim 67, wherein processing through the substrate comprises etching the substrate to transfer the mask pattern into the substrate.

71. The method of claim 67, wherein consolidating the first set of mask features and the plurality of spacers on the same level comprises transferring the first set of mask features and the plurality of spacers into a masking layer overlying the substrate.

72. The method of claim 71, wherein the masking layer comprises amorphous carbon.

73-77. -77. (canceled)