Electronic circuit protection device

• US 20060273813A1
• Filed: 04/20/2006
• Published: 12/07/2006
• Est. Priority Date: 04/21/2005
• Status: Active Grant

• Current Assignee: Stmicroelectronics France (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Coffy, Romain
• Granted Patent: US 7,282,906 B2
• Time in Patent Office: Days
• US Class Current: 361/809
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73207 Bump and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/055 the leads having a passage through the base H01L23/057 takes precedence
• CPC Class Codes: H01L 23/06 characterised by the material of the container or its electrical properties
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H05K 1/0218 : by printed shielding conductors, ground planes or power plane H05K1/0236 takes precedence
• CPC Class Codes: H05K 2203/041 : Solder preforms in the shape of solder balls
• CPC Class Codes: H05K 3/284 : for encapsulating mounted components H05K1/185 takes precedence
• CPC Class Codes: H05K 9/0022 : of components mounted on printed circuit boards [PCB] shields integrated within component packages H01L23/552; shields integrated within PCB H05K1/0218

Abstract

A device for protecting an electronic circuit comprising a support to which are attached at least two circuit portions, each comprising at least one integrated circuit chip. The device comprises a wafer of a semiconductor material covered with a conductive layer arranged parallel to the support, the wafer being connected to the support by conductive pillars distributed around each circuit portion and in contact with the conductive layer.

Claims

1. A device for protecting an electronic circuit that includes a support to which are attached at least two circuit portions, each including at least one integrated circuit chip, comprising:

a wafer of a semiconductor material;

a conductive layer arranged parallel to the support and covering a surface of the wafer; and

conductive pillars connecting the wafer to the support, the conductive pillars being distributed around each circuit portion and in contact with the conductive layer.

2. The device of claim 1, wherein several adjacent conductive pillars are spaced apart, the device further comprising an insulating region arranged at least between the wafer and the support and covering each circuit portion.

3. The device of claim 1, wherein the support comprises:

a planar insulating portion;

first conductive tracks arranged on a first surface of the planar insulating portion, the first conductive tracks being connected to at least some of the conductive pillars;

second conductive tracks arranged on a second surface of the planar insulating portion opposite to the first surface, the second conductive tracks being for connection to a reference voltage; and

means, contained in the planar insulating portion, for connecting the first conductive tracks to the second conductive tracks.

4. The device of claim 1, wherein the conductive pillars have a spherical shape.

5. The device of claim 1, wherein the conductive pillars have an at least partly cylindrical shape.

6. The device of claim 1, wherein at least two adjacent conductive pillars are in contact.

7. The device of claim 1, wherein the support is a ball grid array package.

8. A method for manufacturing electronic circuits, comprising the steps of:

providing a planar support;

attaching on a surface of the support circuit portions, each containing at least one integrated circuit chip;

attaching, parallel to said surface of the support, wafer portions of a semiconductor material, each wafer portion covering at least two adjacent circuit portions, being covered with a metal layer on the side of said at least two adjacent circuit portions, and being connected to the support by conductive pillars distributed around each of said at least two adjacent circuit portions; and

delimiting electronic circuits, each comprising at least two adjacent circuit portions and the associated wafer portion.

9. The method of claim 8, wherein at least several adjacent conductive pillars are spaced apart and the delimiting step is preceded by introducing an insulating material between spaced apart portions of the conductive pillars and under each wafer portion to cover said at least two adjacent circuit portions.

10. The method of claim 8, wherein the wafer portions are obtained by sawing of a wafer on which the conductive pillars are distributed.

11. The method of claim 8 wherein the conductive pillars are formed by spreading welding paste through a mask on to the metal layer.

12. The method of claim 8 wherein the conductive pillars are formed by forming an insulating layer on the metal layer, etching the insulating layer to form openings, and forming the conductive pillars in the openings.

13. A protected electronic device, comprising:

a support;

first and second circuit portions positioned on the support, each circuit portion including at least one integrated circuit chip;

a wafer;

a conductive layer arranged parallel to the support and covering a surface of the wafer; and

conductive pillars connecting the wafer to the support, the conductive pillars being distributed around each circuit portion and in contact with the conductive layer.

14. The device of claim 13, wherein several adjacent conductive pillars are spaced apart, the device further comprising an insulating region arranged at least between the wafer and the support and covering each circuit portion.

15. The device of claim 13, wherein the support comprises:

a planar insulating portion;

first conductive tracks arranged on a first surface of the planar insulating portion, the first conductive tracks being connected to at least some of the conductive pillars;

second conductive tracks arranged on a second surface of the planar insulating portion opposite to the first surface, the second conductive tracks being for connection to a reference voltage; and

conductive vias extending through the planar insulating portion and connecting the first conductive tracks to the second conductive tracks.

16. The device of claim 13, wherein the conductive pillars have a spherical shape.

17. The device of claim 13, wherein the conductive pillars have an at least partly cylindrical shape.

18. The device of claim 13, wherein at least two adjacent conductive pillars are in contact.

19. The device of claim 13, wherein the conductive pillars are distributed around four sides of each of the circuit portions.

20. The device of claim 13 wherein the wafer is of semiconductor material.