Master latch circuit with signal level displacement for a dynamic flip flop
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Abstract
A master latch circuit (10) with signal level displacement for a flip-flop (1) clocked by a clock pulse signal (Clk), wherein the master latch circuit (10) comprises a signal delay circuit (13) which delays and inverts the clock pulse signal (ClK) resulting in a specific time delay (AT), and a circuit node (14) which, in a charging phase wherein the clock pulse signal (Clk) is logically low, is charged to an operational voltage (VB) an which, in an evaluation phase when the clock pulse signal (Clk) and delayed, inverted clock pulse signal (Clk<SB>DELAY</SB>) are logically high, is discharged according to a specific data signal (D), wherein the data signal controls only transistors of a single type (either only N-channel or only P-channel). The master latch circuit (10) has only one supply voltage.
15 Citations
42 Claims
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1-22. -22. (canceled)
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23. A signal level displacement circuit for a flip flop operable to be clocked by a clock signal, the signal level displacement circuit comprising:
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a signal delay circuit configured to generate a delayed clock signal corresponding to the clock signal delayed by a time delay;
a circuit node arranged to charge to an operating voltage in a charging phase in response to the clock signal being logically low and to discharge in an evaluation phase depending on a data signal in response to the clock signal being logically high and the delayed clock signal being logically high; and
a capacitor having a programmable capacitance coupling the circuit node to a reference potential. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 42)
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40. A method, comprising:
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using a clocked isolating circuit to isolate a master latch circuit of an edge triggered flip flop from a slave latch circuit of the flip flop; and
buffer-storing an output signal of the master latch circuit with the slave latch circuit.
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41. A flip flop operable to use a data signal and a clock signal, the flip flop comprising:
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a signal delay circuit configured to generate a delayed clock signal corresponding to the clock signal delayed by a time delay;
a capacitor configured to generate a programmable capacitance;
a controllable switch operably coupled between the signal delay circuit and the capacitor; and
a master latch circuit incorporating at least one of the signal delay circuit, the capacitor, and the controllable switch;
wherein the master latch circuit is configured to charge the capacitor in response to the clock signal being logically low and the master latch circuit is further configured to discharge the capacitor in response to a combination of the clock signal being logically high, the delayed clock signal being logically high, and a state of the data signal.
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Specification