System for controlling integration times of photosensors in an imaging device

• US 20060274174A1
• Filed: 06/02/2005
• Published: 12/07/2006
• Est. Priority Date: 06/02/2005
• Status: Active Grant

• Current Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Original Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Inventors: Tewinkle, Scott L.
• Granted Patent: US 8,411,182 B2
• Time in Patent Office: Days
• US Class Current: 348/297
• CPC Class Codes: H04N 23/60 Control of cameras or camera modules
• CPC Class Codes: H04N 23/667 Camera operation mode switching, e.g. between still and video, sport and normal or high- and low-resolution modes
• CPC Class Codes: H04N 23/84 for processing colour signals
• CPC Class Codes: H04N 25/11 Arrangement of colour filter arrays [CFA]; Filter mosaics
• CPC Class Codes: H04N 25/533 by using differing integration times for different sensor regions
• CPC Class Codes: H04N 25/70 SSIS architectures; Circuits associated therewith

Abstract

A photosensor chip, such as used in a hard-copy scanner, reads out image data in repeated cycles. With each cycle an on-board counter counts to a predetermined number and resets to zero. When the clock count reaches certain numbers, integration events are initiated with regard to different subsets of photosensors on the chip. The start and stop times of the integrations within each cycle can thus be adjusted via software instructions.

Claims

1. An imaging apparatus, comprising:

a first subset of photosensors;

a counter for repeatedly outputting a clock count to a predetermined maximum number; and

a controller, the controller causing the first subset of photosensors to change an integration state in response to the clock count reaching a predetermined first number.

2. The apparatus of claim 1, the change in integration state being at least one of a start of an integration time and an end of an integration time.

3. The apparatus of claim 1, further comprising

at least one register for retaining a value for the predetermined first number.

4. The apparatus of claim 1, further comprising

at least a portion of a programming path for loading values for the predetermined first number.

5. The apparatus of claim 1, further comprising

a second subset of photosensors;

and

the controller causing the second subset of photosensors to change an integration state in response to the clock count reaching a predetermined second number.

6. The apparatus of claim 5, the first subset of photosensors being associated with a first linear array and the second subset of photosensors being associated with a second linear array.

7. The apparatus of claim 5, the controller being programmable to effectively inactivate the second subset of photosensors.

8. The apparatus of claim 5, the first subset of photosensors being sensitive to a first range of wavelength, and the second subset of photosensors being sensitive to a second range of wavelength.

9. The apparatus of claim 5, the first subset of photosensors, second subset of photosensors, and controller being defined in a single chip.

10. An imaging apparatus, comprising:

a first subset of photosensors, the first subset of photosensors being sensitive to a first range of wavelength and forming a first linear array;

a second subset of photosensors, the second subset of photosensors being sensitive to a second range of wavelength and forming a second linear array;

a counter for repeatedly outputting a clock count to a predetermined maximum number; and

a controller, the controller causing the first subset of photosensors to change an integration state in response to the clock count reaching a predetermined first number and causing the second subset of photosensors to change an integration state in response to the clock count reaching a predetermined second number;

the first subset of photosensors, second subset of photosensors, and controller being defined in a single chip;

at least a portion of a programming path for loading values for the predetermined first number and the predetermined second number; and

at least one register for retaining values for the predetermined first number and the predetermined second number.

11. A method of operating an imaging apparatus, the apparatus having a first subset of photosensors, comprising:

outputting a clock count to a predetermined maximum number;

as a result of the clock count reaching a first number, changing an integration state of the first subset of photosensors.

12. The method of claim 11, further comprising

as a result of the clock count reaching a second number, changing an integration state of the first subset of photosensors;

the first number and the second number relating to an integration time of the first subset of photosensors.

13. The method of claim 11, further comprising

as a result of the clock count reaching a third number, causing a readout from the first subset of photosensors.

14. The method of claim 11, further comprising

resetting the clock count after the clock count reaches the predetermined maximum number.

15. The method of claim 11, the apparatus further having a second subset of photosensors, and further comprising

as a result of the clock count reaching a fourth number, changing an integration state of the second subset of photosensors;

as a result of the clock count reaching a fifth number, changing an integration state of the second subset of photosensors;

the fourth number and the fifth number relating to an integration time of the second subset of photosensors.

16. The method of claim 15, the first subset of photosensors being associated with a first linear array and the second subset of photosensors being associated with a second linear array.

17. The method of claim 15, the first subset of photosensors being sensitive to a first range of wavelength, and the second subset of photosensors being sensitive to a second range of wavelength.

18. The method of claim 15, further comprising

selecting the fourth number and the fifth number to effectively inactivate the second subset of photosensors.

19. The method of claim 15, further comprising

as a result of the clock count reaching a sixth number, causing a readout from the second subset of photosensors.

20. An imaging apparatus, comprising:

a first chip, having a first subset of photosensors;

a second chip, having a second set of photosensors;

at least one counter for repeatedly outputting a clock count to a predetermined maximum number; and

the first chip outputting a set of image signals from the first subset of photosensors in response to the clock count reaching a predetermined first number and the second chip outputting a set of image signals from the second subset of photosensors in response to the clock count reaching a predetermined second number.

21. The apparatus of claim 20, wherein the predetermined second number is of a relationship to the first predetermined number such that an output of image signals from the second chip follows an output of image signals from the first chip.

22. The apparatus of claim 20, the first chip having a counter thereon.

23. The apparatus of claim 20, the first chip having a first counter thereon and the second chip having a second counter thereon.

24. The apparatus of claim 20, the first chip having at least one register for retaining a value for the predetermined first number.

25. The apparatus of claim 20, the first chip having at least a portion of a programming path for loading values for the predetermined first number.

26. The apparatus of claim 20, wherein the first subset of photosensors and the second set of photosensors are substantially co-linear.