Reference scheme for a non-volatile semiconductor memory device
First Claim
1. A non-volatile semiconductor memory device comprising:
- a memory area and a circuitry area, wherein said memory area comprises;
a plurality of memory cells arranged in a memory array; and
a set of programmable array reference cells that are provided as references for reading said memory cells, and wherein said circuitry area comprises;
a set of main reference cells that are provided as references for verifying a state of the array reference cells or the memory cells.
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Abstract
A non-volatile semiconductor memory device is provided comprising a memory area and a circuitry area. The memory area includes a plurality of memory cells and a set of array reference cells that are programmable to have a threshold voltage corresponding to an erased or a programmed state of a memory cell. In the circuitry area, additional main reference cells are provided, which are configured to also have a threshold voltage corresponding to an erased or programmed state of a memory cell. The main reference cells are used for setting of said array reference cells and said array reference cells are provided as a reference for reading or writing a state of said memory cells. A method is also provided for setting array reference cells in a non-volatile semiconductor memory device to a predefined threshold voltage.
77 Citations
27 Claims
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1. A non-volatile semiconductor memory device comprising:
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a memory area and a circuitry area, wherein said memory area comprises;
a plurality of memory cells arranged in a memory array; and
a set of programmable array reference cells that are provided as references for reading said memory cells, and wherein said circuitry area comprises;
a set of main reference cells that are provided as references for verifying a state of the array reference cells or the memory cells. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method of operating a non-volatile semiconductor memory device, said memory device comprising:
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a memory area and a circuitry area, wherein said memory area comprises;
a plurality of memory cells arranged in a memory array; and
a set of programmable array reference cells that are provided as references for reading said memory cells, and wherein said circuitry area comprises;
a set of pre-programmed main reference cells that are provided as references for verifying the state of array reference cells or memory cells;
said method comprising;
setting at least one of said array reference cells to a predefined state using at least one of said pre-programmed main reference cells as a reference;
reading the state of at least one memory cell using the at least one of said array reference cells as a reference; and
verifying the state of at least one memory cell when erasing or programming the memory cell using at least one of said main reference cells as a reference. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A method for providing a non-volatile semiconductor memory device comprising:
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providing a plurality of memory cells arranged in a memory array, a set of at least two programmable array reference cells, and a set of at least two programmable main reference cells;
setting at least one of said main reference cells to have a threshold voltage corresponding to an erased state; and
setting at least one other main reference cell to have a threshold voltage corresponding to a programmed state. - View Dependent Claims (26, 27)
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Specification