Adaptive cache design for MPT/MTT tables and TCP context

• US 20060274787A1
• Filed: 09/16/2005
• Published: 12/07/2006
• Est. Priority Date: 06/07/2005
• Status: Abandoned Application

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Pong, Fong
• Application Number:
  US11/228,362
• Publication Number:
  US 20060274787A1
• Time in Patent Office: Days
• US Class Current: 370/469
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 12/145 the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism
• CPC Class Codes: H04L 67/1097 for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
• CPC Class Codes: H04L 69/12 Protocol engines
• CPC Class Codes: H04L 69/16 Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/161 Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields

Abstract

Certain aspects of a method and system for an adaptive cache for memory protection table (MPT), memory translation table (MTT) and TCP context are provided. At least one of a plurality of on-chip cache banks integrated within a multifunction host bus adapter (MHBA) chip may be allocated for storing active connection context for any of a plurality of communication protocols. The MHBA chip may handle a plurality of protocols, such as an Ethernet protocol, a transmission control protocol (TCP), an Internet protocol (IP), Internet small computer system interface (iSCSI) protocol, and a remote direct memory access (RDMA) protocol. The active connection context may be stored within the allocated at least one of the plurality of on-chip cache banks integrated within the multifunction host bus adapter chip, based on a corresponding one of the plurality of communication protocols associated with the active connection context.

Claims

1. A method for processing network data, the method comprising allocating at least one of a plurality of on-chip cache banks integrated within a chip for storing active connection context for any of a plurality of communication protocols, wherein said chip handles a plurality of protocols.

2. The method according to claim 1, wherein said plurality of communication protocols comprises an Ethernet protocol, a transmission control protocol (TCP), an Internet protocol (IP), Internet small computer system interface (iSCSI) protocol, and a remote direct memory access (RDMA) protocol.

3. The method according to claim 1, further comprising storing said active connection context within said allocated at least one of said plurality of on-chip cache banks integrated within said multifunction host bus adapter chip based on a corresponding one of said plurality of communication protocols associated with said active connection context.

4. The method according to claim 1, wherein said allocated at least one of said plurality of on-chip cache banks comprise at least one of:

content addressable memory (CAM) and random access memory (RAM).

5. The method according to claim 1, further comprising receiving within said integrated multifunction host bus adapter chip, at least one search key for selecting said active connection context stored within said at least one of said plurality of on-chip cache banks integrated within said multifunction host bus adapter chip.

6. The method according to claim 5, wherein said at least one search key comprises at least one of:

a symbolic tag (STag), a memory translation table (MTT) entry, and a TCP 4-tuple (lip, lp, fip, fp).

7. The method according to claim 5, further comprising, if said received at least one search key comprises an STag, selecting from within said integrated multifunction host bus adapter chip, at least one memory protection table (MPT) entry stored within said at least one of said plurality of on-chip cache banks, based on said STag.

8. The method according to claim 5, further comprising, if said received at least one search key comprises a memory translation table (MTT) entry, selecting from within said integrated multifunction host bus adapter chip, MTT entry content stored within said at least one of said plurality of on-chip cache banks integrated with multifunction host bus adapter chip, based on said MTT entry.

9. The method according to claim 5, further comprising, if said received at least one search key comprises a TCP 4-tuple (lip, lp, fip, fp), selecting from within said integrated multifunction host bus adapter chip, at least one TCB context entry stored within said at least one of said plurality of on-chip cache banks integrated with multifunction host bus adapter chip, based on said TCP 4-tuple (lip, lp, fip, fp).

10. The method according to claim 5, further comprising enabling from within said integrated multifunction host bus adapter chip, at least one of said plurality of on-chip cache banks integrated within said multifunction host bus adapter chip for said selecting said active connection context.

11. The method according to claim 1, wherein said chip comprises a multifunction host bus adapter chip.

12. A system for processing network data, the system comprising a chip comprising a plurality of on-chip cache banks that allocates at least one of said plurality of on-chip cache banks for storing active connection context for any of a plurality of communication protocols, wherein said chip handles a plurality of protocols.

13. The system according to claim 12, wherein said plurality of communication protocols comprises an Ethernet protocol, a transmission control protocol (TCP), an Internet protocol (IP), Internet small computer system interface (iSCSI) protocol, and a remote direct memory access (RDMA) protocol.

14. The system according to claim 12, wherein said chip stores said active connection context within said allocated at least one of said plurality of on-chip cache banks based on a corresponding one of said plurality of communication protocols associated with said active connection context.

15. The system according to claim 12, wherein said allocated at least one of said plurality of on-chip cache banks comprise at least one of:

content addressable memory (CAM) and random access memory (RAM).

16. The system according to claim 12, wherein said chip receives at least one search key for selecting said active connection context stored within said at least one of said plurality of on-chip cache banks.

17. The system according to claim 16, wherein said at least one search key comprises at least one of:

a symbolic tag (STag), a memory translation table (MTT) entry, and a TCP 4-tuple (lip, lp, fip, fp).

18. The system according to claim 16, wherein said chip selects from within said chip, at least one memory protection table (MPT) entry stored within said at least one of said plurality of on-chip cache banks based on a Stag, if said received at least one search key comprises said STag.

19. The system according to claim 16, wherein said chip selects MTT entry content stored within said at least one of said plurality of on-chip cache banks based on an MTT entry, if said received at least one search key comprises a memory translation table (MTT) entry.

20. The system according to claim 16, wherein said chip selects at least one TCB context entry stored within said at least one of said plurality of on-chip cache banks based on a TCP 4-tuple (lip, lp, fip, fp), if said received at least one search key comprises said TCP 4-tuple (lip, lp, fip, fp).

21. The system according to claim 16, wherein said chip enables at least one of said plurality of on-chip cache banks for said selecting said active connection context.

22. The system according to claim 12, wherein said chip comprises a multifunction host bus adapter chip.