CMOS image sensor and method for fabricating the same

• US 20060275944A1
• Filed: 06/05/2006
• Published: 12/07/2006
• Est. Priority Date: 06/03/2005
• Status: Abandoned Application

• Current Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Original Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Inventors: Hyun, Kim Seoung
• Application Number:
  US11/446,659
• Publication Number:
  US 20060275944A1
• Time in Patent Office: Days
• US Class Current: 438/70
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14625 Optical elements or arrangements associated with the device
• CPC Class Codes: H01L 27/14645 Colour imagers
• CPC Class Codes: H01L 27/14685 Process for coatings or optical elements
• CPC Class Codes: H01L 27/14689 MOS based technologies

Abstract

A CMOS image sensor and a method of fabricating the same are provided. The CMOS image sensor can incorporate one or more photodiodes formed on a substrate at a regular interval, an interlayer insulating layer formed on the substrate; one or more trenches in the interlayer insulating layer at predetermined locations corresponding to the photodiodes, a color filter layer formed in each of the trenches; and at least one microlens corresponding to a color filter layer formed on the resulting substrate. The sensitivity of the CMOS image sensor is improved by reducing the thickness of the CMOS image sensor by forming the trenches in the interlayer insulating layer and forming the color filters in the trenches.

Claims

1. A CMOS (complementary metal oxide silicon) image sensor, comprising:

one or more photodiodes formed on a substrate at a regular interval;

an interlayer insulating layer formed on the substrate;

one or more trenches formed in the interlayer insulating layer at predetermined locations corresponding to the one or more photodiodes;

a color filter layer formed in each of the one or more trenches; and

one or more microlenses formed on the resulting substrate.

2. The CMOS image sensor according to claim 1, further comprising a passivation layer formed in the one or more trenches.

3. The CMOS image sensor according to claim 2, wherein the color filter layer is formed on the passivation layer formed in the one or more trenches.

4. The CMOS image sensor according to claim 2, wherein the passivation layer is formed of SiN.

5. The CMOS image sensor according to claim 1, further comprising a planarizing layer formed on the color filter layer and below the one or more microlenses.

6. The CMOS image sensor according to claim 5, wherein the thickness of the planarizing layer is less than about 100 Å

.

7. The CMOS image sensor according to claim 1, further comprising at least one light-shielding layer formed between adjacent photodiodes.

8. The CMOS image sensor according to claim 7, wherein the at least one light-shielding layer is made of an opaque dielectric material or an opaque metal material.

9. The CMOS image sensor according to claim 1, wherein the depth of the one or more trenches in the interlayer insulating layer is in a range from 3000 Å

to 7000 Å

if a top metal line is not above the one or more photodiodes.

10. The CMOS image sensor according to claim 1, wherein the depth of the one or more trenches in the interlayer insulating layer is in a range from 2000 Å

to 3000 Å

if a top metal line is above the one or more photodiodes.

11. A method of fabricating a CMOS image sensor, comprising:

forming one or more photodiodes on a substrate at a regular interval;

forming an interlayer insulating layer on the substrate having the one or more photodiodes;

forming one or more trenches in the interlayer insulating layer corresponding to the one or more photodiodes;

forming a color filter layer in each of the one or more trenches; and

forming one or more microlenses on the resulting substrate.

12. The method according to claim 11, further comprising forming a passivation layer in the one or more trenches.

13. The method according to claim 12, wherein the color filter layer is formed on the passivation layer formed in the one or more trenches.

14. The method according to claim 12, wherein the passivation layer is formed of SiN.

15. The method according to claim 11, further comprising planarizing the color filter layer.

16. The method according to claim 11, further comprising forming a planarizing layer above the color filter layer and below the one or more microlenses.

17. The method according to claim 11, wherein forming the one or more trenches comprises etching the interlayer insulating layer to form the depth of the trenches in a range from 3000 Å

to 7000 Å

if a top metal line is not included above the one or more photodiodes.

18. The method according to claim 11, wherein forming of the one or more trenches comprises etching the interlayer insulating layer to form the depth of the trenches in a range from 2000 Å

to 3000 Å

if a top metal line is included above the one or more photodiodes.

19. The method according to claim 11, wherein forming the one or more trenches comprises dry etching the interlayer insulating layer using RIE.

20. The method according to claim 11, further comprising forming at least one light-shielding layer on the substrate between adjacent photodiodes.