Three-dimensional integrated circuit structure and method of making same

• US 20060275962A1
• Filed: 03/17/2006
• Published: 12/07/2006
• Est. Priority Date: 06/24/2003
• Status: Abandoned Application

• Current Assignee: BeSang Inc.
• Original Assignee: BeSang Inc.
• Inventors: Lee, Sang-Yun
• Application Number:
  US11/378,059
• Publication Number:
  US 20060275962A1
• Time in Patent Office: Days
• US Class Current: 438/152
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 28/55 with a dielectric comprising a perovskite structure material
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/8613 Mesa PN junction diodes
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
• CPC Class Codes: H10B 53/30 characterised by the memory core region
• CPC Class Codes: H10B 61/22 : of the field-effect transistor [FET] type
• CPC Class Codes: H10B 63/34 : of the vertical channel field-effect transistor type
• CPC Class Codes: H10B 69/00 : Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Vertically oriented semiconductor devices may be added to a separately fabricated substrate that includes electrical devices and/or interconnect. The plurality of vertically oriented semiconductor devices are physically separated from each other, and are not disposed within the same semiconductor body, or semiconductor substrate. The plurality of vertically oriented semiconductor devices may be added to the separately fabricated substrate as a thin layer including several doped semiconductor regions which, subsequent to attachment, are etched to produce individual doped stack structures. Alternatively, the plurality of vertically oriented semiconductor devices may be fabricated prior to attachment to the separately fabricated substrate. The doped stack structures may form the basis for diodes, capacitors, n-MOSFETs, p-MOSFETs, bipolar transistors, and floating gate transistors. Ferroelectric memory devices, Ferromagnetic memory devices, chalcogenide phase change devices, may be formed in a stackable add-on layer for use in conjunction with a separately fabricated substrate. Stackable add-on layers may include interconnect lines.

Claims

1-20. -20. (canceled)

21. A method, comprising:

forming a detach layer below a surface of a first substrate; and

forming at least one pn junction between the detach layer and surface of the first substrate.

22. The method of claim 21, wherein the pn junction includes single crystal semiconductor material.

23. The method of claim 21, further including forming a conductive layer on the surface of the first substrate.

24. The method of claim 23, further including providing an inter-layer dielectric layer with a second conductive layer on its surface.

25. The method of claim 24, further including bonding the first and second conductive layers together.

26. The method of claim 25, further including removing a portion of the first substrate between the detach layer and an opposed surface of the first substrate.

27. The method of claim 21, wherein the detach layer includes an oxide or porous semiconductor region.

28. The method of claim 21, wherein the pn junction is formed between blanket layers of oppositely doped semiconductors.

29. A method, comprising:

providing a first substrate having a detach layer below its surface and a first plurality of differently doped semiconductor layers between the detach layer and surface of the first substrate;

providing a second substrate which carries an inter-layer dielectric layer having a via and interconnection line; and

bonding the inter-layer dielectric layer to the first substrate.

30. The method of claim 29, further including providing a first conductive layer on the substrate so that the inter-layer dielectric layer and first substrate are bonded through the first conductive line.

31. The method of claim 29, further including removing a portion of the first substrate so that the first plurality of differently doped semiconductor layers are carried by the second substrate.

32. The method of claim 31, further including providing a second conductive layer on an exposed surface of the first plurality of differently doped semiconductor layers.

33. The method of claim 32, further including providing a third substrate having a detach layer below its surface and a second plurality of differently doped semiconductor layers between the detach layer and surface of the third substrate.

34. The method of claim 33, wherein the first and second plurality of differently doped semiconductor layers are blanket layers.

35. The method of claim 33, further including providing a third conductive layer on the surface of the third substrate.

36. The method of claim 35, further including bonding the third substrate to the first plurality of differently doped semiconductor layers through the second and third conductive layers.

37. The method of claim 36, further including removing a portion of the third substrate so that the second plurality of differently doped semiconductor layers is carried by the second substrate.

38. The method of claim 37, wherein the first and second plurality of differently doped semiconductor layers include single crystal semiconductor material.

39. The method of claim 29, wherein the detach layer is formed by implanting hydrogen.

40. A method, comprising:

providing a substrate which carries a first inter-layer dielectric layer;

providing a first stackable add-on layer;

bonding the first stackable add-on layer to the first inter-layer dielectric layer; and

processing the first stackable add-on layer to form a first vertically oriented semiconductor device.

41. The method of claim 40, wherein the first stackable add-on layer includes single crystalline semiconductor material.

42. The method of claim 40, wherein the first vertically oriented semiconductor device includes a stack of differently doped semiconductor layers.

43. The method of claim 42, further including forming a gate dielectric around the stack of differently doped semiconductor layers, and forming a gate electrode around the gate dielectric.

44. The method of claim 43, wherein the gate dielectric is formed at a temperature below about 650°

C.

45. The method of claim 43, wherein the gate electrode includes a metal.

46. The method of claim 43, wherein the stack of differently doped semiconductor layers, gate dielectric, and gate electrode operate as a memory device.

47. The method of claim 43, wherein the gate dielectric includes an oxide-nitride-oxide layer stack of materials.