Apparatus and method for coupling a plurality of test access ports to external test and debug facility

• US 20060277436A1
• Filed: 04/26/2006
• Published: 12/07/2006
• Est. Priority Date: 04/27/2005
• Status: Active Grant

• Current Assignee: Robert A. Mcgowan
• Original Assignee: Robert A. Mcgowan
• Inventors: McGowan, Robert A.
• Granted Patent: US 7,676,698 B2
• Time in Patent Office: Days
• US Class Current: 714/30
• CPC Class Codes: G06F 11/2236 to test CPU or processors

Abstract

An interface unit is provided in a JTAG test and debug procedure involving a plurality of processor cores. The interface unit includes a TAP unit. A switch unit is coupled to the interface unit and switch units are coupled to each of the plurality of processor/cores. The switch units are coupled in series and have the TDI signal and the TCLK signal applied to the first switch unit. In response to first control signals, the switch unit can either transmit the TDI signals applied to the input terminal through the associated TAP unit to a switch unit output terminal or apply TDI signals directly to the output terminal. Similarly, the TCLK signal can be short-circuited across a switch unit or applied to the TAP unit and a RTCLK can controllably applied to the switch unit output terminal. The interface unit includes a logic unit that permits signals from the TAP unit to provide control signals to each of the switch units. The interface unit includes a plurality of status and control registers, the status registers including the power, clock and security status of an associated processor/core. The status of each processor/core is available to the test and debug unit through the TAP unit of the interface unit.

Claims

1. An interface unit for providing an interface between a plurality of processor/core and a test and debug unit, the processor/cores having TAP unit, the TAP units having switch unit coupled in parallel therewith;

the interface unit comprising;

an interface TAP unit; and

a switch unit coupled in parallel with the interface TAP unit, wherein the switch unit has a first state connecting an input and an output terminal in response to a first control signal, the switch having a second state coupling the input terminal and the output terminal through the TAP unit in response to a second control signal, the switch units being coupled in series; and

a logic unit responsive to signals from the interface TAP unit for generating control signals determining the state of each switch.

2. The interface unit as recited in claim 1 wherein the control signals generate a configuration of at least TAP unit coupled in series for receiving the TDI signal and returning the TDO signal.

3. The interface unit as recited in claim 1 wherein the control signals generate a series configuration of at least one TAP unit for receiving the TDI signal and returning the TDO signal.

4. The interface unit as recited in claim 3 wherein in response to first control signals, the switches can apply the TCLK signal through each TAP unit included in the scan chain.

5. The interface unit as recited in claim 1 further comprising a plurality of status and control registers coupled to the interface TAP unit, the status registers including status information with respect to the processor/cores, the status information being transmitted to the test and debug apparatus.

6. The interface unit as recited in claim 4 wherein the status information for the processor/cores includes at one information type selected from the group consisting of clock information, power information, and security information.

7. The interface unit as recited in claim 1 wherein the interface unit is responsive to signals from a security state machine, the security status signals determining the availability for test and debug procedures.

8. The interface unit as recited in claim 1 wherein each processor/core has a power state machine coupled thereto, each power state machine determining the power being applied to the coupled processor/core.

9. A method for the test and debug of a plurality of processor/cores, the method comprising:

selecting at least one processor/core for test and debug;

coupling the selected TAP units of the selected processor/cores in series with a test and debug apparatus;

entering predetermined signals into the series of TAP units; and

analyzing resulting signals extracted from the series of TAP units resulting from the predetermined signals

10. The method as recited in claim 9 further comprising:

determining the selected processor/core TAP units by control signals from an interface unit, wherein the interface unit includes an interface TAP unit.

11. The method as recited in claim 9 further comprising:

storing status signals in the interface unit; and

communicating the status signals to the test and debug apparatus through the interface TAP unit.

12. The method as recited in claim 9 wherein the entering predetermined signals includes entering TDI signals.

13. The method as recited in claim 9 wherein the entering step includes entering TCLK signals into selected processor/cores.

14. A test and debug system, the system comprising:

a test and debug unit;

a plurality of processor/cores, each processor/core having a TAP unit,

an interface unit, the interface unit including an interface TAP unit, the interface unit including a logic unit;

a second plurality of switch units coupled in series, each TAP unit and interface unit having a switch coupled there to, each switch having first state connecting the input terminal with the output terminal, the switches having a second state coupling the input terminal and the output terminal through the coupled TAP unit, wherein the state of each switch is determined by control signals from the logic unit, the control signals generated in response to the signals applied to the interface TAP unit.

15. The system as recited in claim 14 wherein the interface unit includes status registers, values in the status registers reflecting the status of an associated processor/core.

16. The system as recited in claim 15 wherein the values in the status register designate at least one parameter selected from the group consisting of clock parameters, power parameters, and security parameters.

17. The system as recited in claim 14 wherein TDI signals are entered in the selected TAP units,

18. The system as recited in claim 14 wherein TCLK signals are entered in each selected processor/core by means of the coupled switch units.

19. The system as recited in claim 16 wherein the values in the status registers determine the selected processor/cores.

20. The system as recited in claim 14 further comprising a security state machine coupled to the logic unit, the security state machine storing the security status of the processor/cores, the security status of each processor/core in the state machine being stored in the status registers.