SYSTEM AND METHOD FOR ANALYZING POWER CONSUMPTION OF ELECTRONIC DESIGN UNDERGOING EMULATION OR HARDWARE BASED SIMULATION ACCELERATION

• US 20060277509A1
• Filed: 06/05/2006
• Published: 12/07/2006
• Est. Priority Date: 06/03/2005
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Zhu, Bing, Lin, Tsair-Chin, Tung, Tung-sun
• Granted Patent: US 8,453,086 B2
• Time in Patent Office: Days
• US Class Current: 716/109
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

The invention described here is the methods of using a hardware-based functional verification system to mimic a design under test (DUT), under intended application environment and software, to record or derive the transition activities of all circuits of the DUT, then calculate the total or partial power consumption during the period of interest. The period of interest is defined by the user in terms of “events” which are the arbitrary states of the DUT. Furthermore, the user can specify the number of sub-divisions required between events thus vary the apparent resolution of the power consumption profile.

Claims

1. A method for calculating power consumption of a logic design comprising:

running the logic design in a hardware-based functional verification system;

collecting state transition data for each logic gate and register in the logic design for state transitions taking place during a first sample period, said first sample period comprising a first predetermined number of clock cycles; and

calculating power consumed by the logic design using the state transition data collected during said first sample period.

2. The method of claim 1 further comprising:

collecting state transition data for each logic gate and register in the logic design for state transitions taking place during a second sample period, said second sample period comprising a second predetermined number of clock cycles;

calculating power consumed by the logic design using the state transition data collected during said second sample period; and

plotting power consumption calculated for said first sample period and said second sample period on a graph, thereby displaying power consumed by the logic design.

3. The method of claim 1 wherein said state transition data further comprises duty cycle data.

4. A method for calculating power consumption of a logic design comprising:

defining a power event, said power event defined by a triggering condition comprising predetermined state conditions for specified nodes in the logic design,

defining a sampling window, said sampling window comprising a plurality of segments, each of said samples defining how many cycles of a clock driving the logic design for which circuit transition data for each logic gate and register in the logic design will be collected;

running the logic design in a functional verification system;

when said power event is triggered, collecting said state transition data; and

calculating power consumed by the logic design using the state transition data collected during each of said plurality of samples; and

plotting power consumption calculated for each of said plurality of segments on a graph, thereby displaying power consumed by the logic design.

5. A method for calculating power consumption of a logic design comprising:

running the logic design in a functional verification system;

collecting state transition data for each logic gate and register in the logic design while the logic design is emulated over a power evaluation period;

dividing said power evaluation period into a plurality of windows, wherein each of said plurality of windows is defined by a predetermined number of segments, each of said segments comprising state transition data for a number of clock cycles taking place during a time period while the logic design was run in said functional verification system;

calculating power consumed by the logic design using the state transition data for each of said segments; and

plotting power consumption calculated for each of said plurality of segments on a graph, thereby displaying power consumed by the logic design.

6. The method of claim 5 wherein during periods of low power consumption, said windows have fewer segments than during periods of higher power consumption.

7. The method of claim 5 wherein during periods of high power consumption, said windows have more segments than during periods of low power consumption.

8. The method of claim 5 wherein said windows are comprised of segments that collect state transition data for a smaller number of clock cycles than during periods of lower power consumption.