Charge mode active pixel sensor read-out circuit

• US 20060278812A1
• Filed: 06/20/2006
• Published: 12/14/2006
• Est. Priority Date: 07/09/2001
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Rossi, Giuseppe, Barna, Sandor L.
• Granted Patent: US 7,649,558 B2
• Time in Patent Office: Days
• US Class Current: 250/208.100
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/41 Extracting pixel data from a plurality of image sensors simultaneously picking up an image, e.g. for increasing the field of view by combining the outputs of a plurality of sensors
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Abstract

An apparatus such as an imager includes groups of sensors each of which includes subgroups of sensors. Subgroup select circuits are coupled to outputs from respective subgroups of sensors, and group select circuits are coupled to outputs from subgroup select circuits associated with respective ones of the groups. A bus is coupled to receive outputs from the group select circuits. A controller can provide control signals to the subgroup select circuits and the group select circuits to selectively enable the respective subgroup select circuits and group select circuits to pass signals from the sensors to the bus one sensor at a time.

Claims

1-23. -23. (canceled)

24. An integrated circuit comprising:

a plurality of first sets of pixels, each first set comprising a plurality of subsets of pixels;

a plurality of first circuits each coupled to an output from a respective subset;

a plurality of second circuits, each of which is coupled to outputs from the first circuits associated with a respective one of the first sets;

a first bus for each first set coupled to the outputs of the associated first circuits, each first circuit configured to selectively connect the respective subset to a respective first bus;

a second bus for receiving signals from each of the sets, each second circuit configured to selectively connect the respective set to the respective second bus;

a readout circuit for receiving signals from the first and second buses; and

a third circuit coupled to each first bus for selectively isolating each first set from the readout circuit, the third circuit comprising a first switch for selectively connecting the first bus to a predetermined voltage.

25. The integrated circuit of claim 24 further comprising a controller for providing control signals to the first circuits and the second circuits to selectively enable the respective first circuits and second circuits to pass signals in a charge mode manner from the pixels to the readout circuit.

26. The integrated circuit of claim 24 further comprising a second bus coupled to the outputs of the second circuits and the readout circuit.

27. The integrated circuit of claim 24 wherein the number of second circuits is approximately equal to the square root of the number of first circuits.

28. The integrated circuit of claim 24 wherein a ratio of the number of first circuits to second circuits is in a range of 10:

1 and 40;

1.

29. The integrated circuit of claim 24 wherein each first circuit comprises a transistor switch with a respective gate terminal for receiving a control signal from the controller, wherein when the transistor switch is turned on, the second circuit is enabled to pass signals from associated first circuits to the first bus.

30. The integrated circuit of claim 29 wherein each first circuit comprises a transistor switch with a respective gate terminal for receiving a control signal from the controller, wherein when the first circuit transistor switch is turned on, the first circuit is enabled to pass signals from an associated subset of pixels.

31. The integrated circuit of claim 24 wherein each second circuit comprises a pair of NMOS transistor switches.

32. The integrated circuit of claim 24 further comprising:

a plurality of second sets of pixels, each second set comprising at least two first sets;

fourth circuits, each of which is coupled to outputs from second circuits associated with a respective one of the second sets, each fourth circuit configured to selectively connect the respective second set to a third bus, the third bus connected to the readout circuit; and

a fifth circuit coupled to each second bus for selectively isolating each second set from the readout circuit, the fifth circuit comprising a second switch for selectively connecting the second bus to a predetermined voltage.

33. The integrated circuit of claim 32 wherein the controller is configured to provide control signals to the fourth circuits to selectively enable the fourth circuits to pass a signal from the second bus to the third bus.

34. The integrated circuit of claim 32 wherein each fourth circuit comprises a transistor switch with a respective gate terminal for receiving a control signal from the controller.

35. An image sensor comprising:

an array of pixels arranged in columns and rows, the array comprising;

a plurality of first sets of pixels, each first set comprising a plurality of subsets of pixels, each subset comprising at least one column of pixels;

a plurality of first circuits each coupled to an output from a respective subset;

a plurality of second circuits, each of which is coupled to outputs from the first circuits associated with a respective one of the first sets;

a first bus for each first set coupled to the outputs of the associated first circuits, each first circuit configured to selectively connect the respective subset to a respective first bus;

a second bus for receiving signals from each of the sets, each second circuit configured to selectively connect the respective set to the respective second bus;

a readout circuit for receiving signals from the first and second buses; and

a third circuit coupled to each first bus for selectively isolating each first set from the readout circuit, the third circuit comprising a first switch for selectively connecting the first bus to a predetermined voltage.

36. The image sensor of claim 35, further comprising:

a plurality of second sets of pixels, each second set comprising at least two first sets;

fourth circuits, each of which is coupled to outputs from second circuits associated with a respective one of the second sets, each fourth circuit configured to selectively connect the respective second set to a third bus, the third bus connected to the readout circuit; and

a fifth circuit coupled to each second bus for selectively isolating each second set from the readout circuit, the fifth circuit comprising a second switch for selectively connecting the second bus to a predetermined voltage.

37. The image sensor of claim 36, wherein the predetermined voltage is one of a supply voltage for the apparatus or a ground potential.

38. An image sensor comprising:

an array of pixels arranged in columns and rows, the pixels of a column having commonly connected outputs;

a plurality of first selector circuits each respectfully associated with a column of pixels, the first selector circuits being arranged into a plurality of first groups of first selector circuits and each first selector circuit of a first group being selectively operable to connect a respective column of pixels to a first bus;

a plurality of second selector circuits each associated with a first bus for selectively connecting an associated first bus to a second bus;

a readout circuit for reading out pixel signals from the first and second buses; and

an isolation circuit for selectively connecting at least one first bus to a predetermined voltage.

39. The image sensor of claim 38, wherein the second selector circuits are arranged into a plurality of second groups of second selector circuits and each second selector circuit of a second group being selectively operable to connect an associated first bus to a respective second bus;

and further comprising a plurality of third selector circuits each associated with a second bus for selectively connecting an associated second bus to a third bus.

40. The image sensor of claim 38, further comprising an isolation circuit for selectively connecting at least one second bus to a predetermined voltage.

41. The image sensor of claim 39, further comprising an isolation circuit for selectively connecting the third bus to a predetermined voltage.

42. The image sensor of claim 39, wherein the readout circuit is coupled to the third bus.

43. A method of obtaining a readout of a pixel sensor array comprising:

providing an array of pixels, the array comprising a plurality of sets of pixels, each set comprising a plurality of subsets of pixels;

selectively enabling a first circuit and a second circuit to allow a signal from each pixel in a subset to pass sequentially and in a charge mode manner to a readout circuit electrically connected to said first circuit, the first circuit connected to an output of each subset, the second circuit connected to an output of each set;

sensing a charge at the readout circuit; and

selectively isolating from the readout circuit the subsets and sets not associated with the selectively enabled first circuit by disabling the second circuits and first circuits not associated with the selectively enabled first circuit and applying a predetermined voltage to at least one first bus coupled to the disabled first circuits by operating a switch coupled to the at least one first bus.

44. The method of claim 43, wherein the pixels are further organized in columns and rows and wherein each subset comprises at least one column.

45. The method of claim 43, wherein the predetermined voltage is one of a supply voltage for the array or a ground potential.