SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20060278875A1
• Filed: 06/02/2006
• Published: 12/14/2006
• Est. Priority Date: 06/10/2005
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: OHNUMA, Hideto, MONOE, Shigeharu, YAMAZAKI, Shunpei
• Granted Patent: US 7,588,970 B2
• Time in Patent Office: Days
• US Class Current: 257/66
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78624 the source and the drain regions being asymmetrical

Abstract

The present invention provides a TFT including at least one LDD region in a self-alignment manner without forming a sidewall spacer and increasing the number of manufacturing steps. A photomask or a reticle provided with an assist pattern that is formed of a diffraction grating pattern or a semi-transmitting film and has a function of reducing light intensity is employed in a photolithography step of forming a gate electrode, an asymmetrical resist pattern having a region with a thick thickness and a region with a thickness thinner than that of the above region on one side is formed, a gate electrode having a stepped portion is formed, and an LDD region is formed in a self-alignment manner by injecting an impurity element to the semiconductor layer through the region with a thin thickness of the gate electrode.

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of:

forming an insulating film over a semiconductor layer,

forming a conductive film over the insulating film,

forming a resist pattern having a first portion with a thick thickness and a second portion with a thickness thinner than that of the first portion on one side over the conductive film by using a photomask or a reticle having a diffraction grating pattern or a semi-transmitting portion,

forming a gate electrode having a first portion with a thick thickness and a second portion with a thickness thinner than that of the first portion on one side by selectively etching the conductive film,

forming first impurity regions arranged on both sides of a channel formation region overlapped with the gate electrode in the semiconductor layer by injecting an impurity element to the semiconductor layer using the first portion with a thick thickness and the second portion with a thin thickness of the gate electrode as a mask, and

forming a second impurity region in a region overlapped with the second portion with a thin thickness of the gate electrode in the semiconductor layer by injecting an impurity element to the semiconductor layer through the second portion with a thin thickness of the gate electrode.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the region overlapped with the first portion with a thick thickness of the gate electrode in the semiconductor layer becomes a channel formation region, and the channel formation region is arranged between the first impurity region and the second impurity region to be in contact.

3. The method for manufacturing a semiconductor device according to claim 1, wherein the conductive film is a staked layer of different conductive materials.

4. The method for manufacturing a semiconductor device according to claim 1, wherein a cross-sectional shape of the resist pattern is asymmetry in a width or a length direction of the gate electrode.

5. A method for manufacturing a semiconductor device, comprising the steps of:

forming an insulating film over a semiconductor layer,

forming a conductive film over the insulating film,

forming a resist pattern having a first portion with a thick thickness and a second portion with a thickness thinner than that of the first portion on one side over the conductive film by using a photomask or a reticle having a diffraction grating pattern or a semi-transmitting portion,

forming a gate electrode having a first portion with a thick thickness and a second portion with a thickness thinner than that of the first portion on one side by selectively etching the conductive film, and

forming first impurity regions on both sides of a channel formation region overlapped with the gate electrode in the semiconductor layer and a second impurity region in a region overlapped with the first portion with a thin thickness of the gate electrode in the semiconductor layer by injecting an impurity element to the semiconductor layer.

6. The method for manufacturing a semiconductor device according to claim 5, wherein the region overlapped with the first portion with a thick thickness of the gate electrode in the semiconductor layer becomes a channel formation region, and the channel formation region is arranged between the first impurity region and the second impurity region to be in contact.

7. The method for manufacturing a semiconductor device according to claim 5, wherein the conductive film is a staked layer of different conductive materials.

8. The method for manufacturing a semiconductor device according to claim 5, wherein a cross-sectional shape of the resist pattern is asymmetry in a width or a length direction of the gate electrode.

9. A semiconductor device in which a first thin film transistor having a first semiconductor layer and a second thin film transistor having a second semiconductor layer are provided over the same substrate, comprising:

the first semiconductor layer over a substrate having an insulating surface and the second semiconductor layer arranged apart from the first semiconductor layer,

a gate insulating layer over the first semiconductor layer and the second semiconductor layer, and

a first gate electrode and a second gate electrode formed by stacked conductive layers over the gate insulating layer,

wherein the first semiconductor layer includes a first channel formation region, two of first impurity regions on both sides of the first channel formation region, and one second impurity region between one of the first impurity regions and the first channel formation region;

wherein the first channel formation region is overlapped with the first gate electrode with the gate insulating layer interposed therebetween,

wherein a first conductive layer forming one layer of the stacked first gate electrode is overlapped with at least the first channel formation region and the second impurity region;

wherein a second conductive layer forming another layer of the stacked first gate electrode is provided over and in contact with the first conductive layer and overlapped with the first channel formation region,

wherein the second semiconductor layer includes a second channel formation region, two of first impurity regions on both sides of the second channel formation region, and second impurity regions each between the first impurity region and the second channel formation region,

wherein the second channel formation region is overlapped with the second gate electrode with the gate insulating layer interposed therebetween,

wherein a first conductive layer forming one layer of the stacked second gate electrode is overlapped with at least the second channel formation region and two of the second impurity regions; and

wherein a second conductive layer forming another layer of the stacked second gate electrode is provided over and in contact with the first conductive layer and overlapped with the second channel formation region.

10. The semiconductor device according to claim 9, wherein the first thin film transistor is electrically connected a pixel electrode,

wherein the first thin film transistor comprises a pixel portion.

11. The semiconductor device according to claim 9, wherein the first thin film transistor comprises a pixel portion,

wherein the second thin film transistor comprises a driver circuit for controlling the pixel portion.

12. The semiconductor device according to claim 9, further comprising a wiring portion including first and second wiring layers in which end portions are in alignment,

wherein the first and second wiring layers are same material as the stacked conductive layers.