Mis transistor and cmos transistor

• US 20060278909A1
• Filed: 06/11/2004
• Published: 12/14/2006
• Est. Priority Date: 06/13/2003
• Status: Abandoned Application

• Current Assignee: Foundation for Advancement of International Science
• Original Assignee: Foundation for Advancement of International Science
• Inventors: Ohmi, Tadahiro, Sugawa, Shigetoshi, Teramoto, Akinobu, Miyagi, Hiroshi, Nishimuta, Takefumi
• Application Number:
  US10/560,706
• Publication Number:
  US 20060278909A1
• Time in Patent Office: Days
• US Class Current: 257/296
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A MIS transistor, formed on a semiconductor substrate, assumed to comprise a semiconductor substrate (702, 910) comprising a projecting part (704, 910B) with at least two different crystal planes on the surface on a principal plane, a gate insulator (708, 920B) for covering at least a part of each of said at least two different crystal planes constituting the surface of the projecting part, a gate electrode (706, 930B), comprised on each of said at least two different crystal planes constituting the surface of the projecting part, which sandwiches the gate insulator with the said at least two different planes, and a single conductivity type diffusion region (710a, 710b, 910c, 910d) formed in the projecting part facing each of said at least two different crystal planes and individually formed on both sides of the gate electrode. Such a configuration allows control over increase in the element area and increase of channel width.

Claims

1. A MIS transistor, formed on a semiconductor substrate, comprising:

a semiconductor substrate comprising a projecting part of which the surfaces are at least two different crystal planes on a principal plane;

a gate insulator for covering at least a part of each of said at least two different crystal planes constituting the surface of the projecting part;

a gate electrode comprised by the gate insulator so as to be electrically insulated from the semiconductor substrate, and comprised on each of said at least two different crystal planes constituting the surface of the projecting part; and

a single conductivity type diffusion region formed in the projecting part facing each of said at least two different crystal planes constituting the surface of the projecting part and individually formed on both sides of the gate electrodes.

2. The MIS transistor according to claim 1 wherein

the channel width of a channel formed along with the gate insulator between the single conductivity diffusion regions individually formed on both sides of the gate electrodes is indicated by summation of the channel widths of each channel generated along said at least two different crystal planes.

3. The MIS transistor according to claim 1 or wherein

the gate insulator covers said at least a part of each of said at least two different crystal planes, which configure the surface of the projecting part, so that said at least two different crystal planes are continuously covered.

4. A MIS transistor, according to claim 2 wherein

the gate insulator covers said at least a part of each of said at least two different crystal planes which configure the surface of the projecting part so that said at least two different crystal planes are continuously covered.

9. The MIS transistor according to claim 1, being a signal transistor.

11. The MIS transistor according to claim 1, wherein

the semiconductor substrate is a silicon substrate and

the gate insulator is formed by exposing the surface of the silicon substrate to a plasma of a prescribed inert gas so as to remove hydrogen and the hydrogen content at an interface of the silicon substrate and the gate insulator is 10¹¹/cm² or less in units of surface density.

13. The MIS transistor according to claim 11, wherein

the semiconductor substrate is a silicon substrate and

the principal plane and said at least two different crystal planes are any two different crystal planes from the (100) plane, the (110) plane and the (111) plane.

14. A CMOS transistor, comprising the MIS transistor according to claim 1, and also comprising an n-channel MOS transistor only formed on a principal plane of a semiconductor substrate and a p-channel MOS transistor, wherein

the p-channel MOS transistor comprises

that the gate insulator is an oxide film, and

that the single conductivity type diffusion region is a p-type diffusion region.

16. A CMOS transistor, comprising the MIS transistor according to claim 11, and also comprising an n-channel MOS transistor only formed on a principal plane of a semiconductor substrate and a p-channel MOS transistor, wherein

the p-channel MOS transistor comprises

that the gate insulator is an oxide film, and

that the single conductivity type diffusion region is a p-type diffusion region.

17. A CMOS transistor comprising the MIS transistor according to claim 1, and also comprising an n-channel MOS transistor and a p-channel MOS transistor on a silicon substrate with the (100) plane as its principal plane, wherein

the n-channel MOS transistor comprises

a gate oxide film covering a part of the principal plane alone,

a gate electrode configured on the principal plane by the gate oxide film so as to be electrically insulated from the silicon substrate, and

an n-type diffusion region formed in the silicon substrate facing the principal plane and formed on both sides of the gate electrode, and

the p-channel MOS transistor comprises

that the single conductivity type diffusion region is a p-type diffusion region;

that the gate insulator is an gate oxide film, and

that one crystal plane is the (100) crystal plane and a second crystal plane is the (110) crystal plane among said at least two crystal planes.

19. The CMOS transistor according to claim 16, wherein the current driving capacity in the p-channel MOS transistor and the n-channel MOS transistor are equal to each other and the element area of the p-channel MOS transistor and the n-channel MOS transistor are the same.

5. The MIS transistor formed on a semiconductor substrate, comprising:

a semiconductor substrate comprising a projecting part of which the surfaces are at least two different crystal planes on a principal plane;

a gate insulator for covering at least a part of each of said at least two different crystal planes constituting the principal plane and the surface of the projecting part;

a gate electrode comprised by the gate insulator so as to be electrically insulated from the semiconductor substrate, and comprised on each of said at least two different crystal planes constituting the principal plane and the surface of the projecting part; and

a single conductivity type diffusion region formed in the projecting part facing each of said at least two different crystal planes constituting the principal plane and surface of the projecting part and individually formed on both sides of the gate electrodes.

6. The MIS transistor according to claim 5, wherein

the gate insulator covers at least a part of each of said at least two different crystal planes, which configure the principal plane and the surface of the projecting part, so that the principal plane and said at least two different crystal planes are continuously covered.

7. The MIS transistor, according to claim 5, wherein

the gate insulator covers at least a part of each of said at least two different crystal planes, which configure the principal plane and the surface of the projecting part, so that the principal plane and said at least two different crystal planes are continuously covered.

8. The MIS transistor according to claim 6, wherein

the gate insulator covers at least a part of each of said at least two different crystal planes, which configure the principal plane and the surface of the projecting part, so that the principal plane and said at least two different crystal planes are continuously covered.

10. The MIS transistor, according to claim 5, being a signal transistor.

12. The MIS transistor according to claim 5, wherein

the semiconductor substrate is a silicon substrate, and

the gate insulator is formed by exposing the surface of the silicon substrate to a plasma of a prescribed inert gas so as to remove hydrogen and the hydrogen content at an interface of the silicon substrate and the gate insulator is 10¹¹/cm² or less in units of surface density.

15. A CMOS transistor, comprising the MIS transistor according to claim 5, and also comprising an n-channel MOS transistor only formed on a principal plane of a semiconductor substrate and a p-channel MOS transistor, wherein

the p-channel MOS transistor comprises

that the gate insulator is an oxide film, and

that the single conductivity type diffusion region is a p-type diffusion region.

18. A CMOS transistor comprising the MIS transistor according to claim 5, and also comprising an n-channel MOS transistor and a p-channel MOS transistor on a silicon substrate with the (100) plane as its principal plane, wherein

the n-channel MOS transistor comprises

a gate oxide film covering a part of the principal plane alone,

a gate electrode configured on the principal plane by the gate oxide film so as to be electrically insulated from the silicon substrate, and

an n-type diffusion region formed in the silicon substrate facing the principal plane and formed on both sides of the gate electrode, and

the p-channel MOS transistor comprises

that the single conductivity type diffusion region is a p-type diffusion region;

that the gate insulator is an gate oxide film, and

that one crystal plane is the (100) crystal plane and a second crystal plane is the (110) crystal plane among said at least two crystal planes.